SN74LS109ADRG4 Texas Instruments Integrated Circuit (Small Outline Packages) In Stock

SN74LS109ADRG4 is a dual positive-edge-triggered J-K flip-flop from Texas Instruments in the LS logic family, featuring an inverted K input (J-Kbar configuration), 16-pin SOIC package, and up to 25 MHz toggle frequency for use in counters, registers, and clocked sequential logic circuits.

OBSOLETEIntegrated CircuitVerified May 2026
Package / Visual Reference
SN74LS109ADRG4Small Outline Packages
Quick Facts
Manufacturer
Texas Instruments
Package
Small Outline Packages
Pin Count
16
Lifecycle
OBSOLETE
Category
Integrated Circuit
Temp Range
?°C to 70.0°C
RoHS
Compliant
Lead Time
3–7 business days
Shipping
DHL Express · Worldwide

Key Features

  • Dual J-Kbar flip-flop with positive edge-triggered clocking
  • Maximum toggle frequency of 25 MHz for sequential logic applications
  • Inverted K input (active-low Kbar) for direct J-K flip-flop implementations
  • LS family logic with 8 mA output sink current per output
  • 16-pin SOIC package compatible with standard small-outline footprints
  • RoHS-compliant (JESD-609 e4) and Pb-free

Applications

SN74LS109ADRG4 is used in synchronous counter chains, shift registers, and state-machine implementations in digital logic designs operating up to 25 MHz. The dual flip-flop configuration allows two independent storage elements in a single 16-pin SOIC package, reducing component count in clock dividers, binary counters, and toggle-mode latch circuits. It is also found in legacy industrial logic boards, FPGA emulation prototypes, and educational digital design lab kits requiring standard LS-family sequential logic.

Specifications

Pbfree CodeYes
YTEOL0
Additional FeatureINVERTED K INPUT
FamilyLS
JESD-30 CodeR-PDSO-G16
JESD-609 Codee4
Logic IC TypeJ-KBAR FLIP-FLOP
Max Frequency@Nom-Sup25000000Hz
Max I(ol)0.008A
Number of Bits2
Number of Functions2
Output PolarityCOMPLEMENTARY
Package Body MaterialPLASTIC/EPOXY
Package Equivalence CodeSOP16,.25
Package ShapeRECTANGULAR
Package StyleSMALL OUTLINE
Packing MethodTR
Peak Reflow Temperature (Cel)260
Power Supply Current-Max (ICC)8mA
Prop. Delay@Nom-Sup40ns
Propagation Delay (tpd)40ns
Qualification StatusNot Qualified
Supply Voltage-Max (Vsup)5.25V
Supply Voltage-Min (Vsup)4.75V
Supply Voltage-Nom (Vsup)5V
Surface MountYES
TechnologyTTL
Temperature GradeCOMMERCIAL
Terminal FinishNICKEL PALLADIUM GOLD
Terminal FormGULL WING
Terminal Pitch1.27mm
Terminal PositionDUAL
Time@Peak Reflow Temperature-Max (s)30
Trigger TypePOSITIVE EDGE
fmax-Min25MHz
PackageSmall Outline Packages

Compliance & Regulatory

RoHS StatusCompliant
Lead-FreeYes (Pb-Free)
Moisture Sensitivity LevelMSL 1
HTS Code8542.39.00.60

Datasheet

SN74LS109ADRG4 Datasheet Download

Official datasheet from Texas Instruments

Alternate & Equivalent Parts

Compatible alternatives and drop-in replacements for SN74LS109ADRG4:

SN74LS109ADTexas Instruments

J-Kbar Flip-Flop, LS Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16

View Part →
SN74LS109ANSRTexas Instruments

J-Kbar Flip-Flop, LS Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16

View Part →

Frequently Asked Questions

At what maximum frequency can SN74LS109ADRG4 operate as a toggle flip-flop?

SN74LS109ADRG4 supports a maximum clock frequency of 25 MHz in toggle mode, making it suitable for counter and divider circuits in systems where the clock domain does not exceed this limit. For applications requiring higher speeds, AHCT or ACT family flip-flops operating above 100 MHz would be a better choice.

How does the inverted K input (Kbar) in SN74LS109ADRG4 affect flip-flop operation compared to a standard JK device?

The Kbar (active-low K) input in SN74LS109ADRG4 means that asserting K low is equivalent to asserting K high on a standard JK flip-flop. When both J is high and Kbar is low (equivalent to K high), the output toggles on the rising clock edge. This inversion simplifies interfacing with active-low control signals from bus logic without requiring an external inverter gate.

How many independent flip-flop elements does SN74LS109ADRG4 provide, and how does that help in counter designs?

SN74LS109ADRG4 contains 2 independent positive-edge-triggered J-Kbar flip-flops in a single 16-pin SOIC package. In a 2-bit binary counter, both flip-flops are used from one IC, halving the IC count compared to single flip-flop packages. Cascading additional SN74LS109ADRG4 devices extends the counter to 4, 6, or more bits while keeping board area compact.

Is SN74LS109ADRG4 appropriate for new designs, or is it mainly a replacement part for legacy boards?

SN74LS109ADRG4 is most commonly specified as a drop-in replacement for legacy LS-family logic on maintenance and repair boards, since its 25 MHz speed limit and 8 mA sink current per output are modest by modern standards. New designs typically prefer faster, lower-power logic families like 74LVC or 74AHC, but for exact pin-compatible substitution in 16-pin SOIC through-hole or surface-mount legacy applications, this device remains widely available.

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About Texas Instruments

Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.

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Lead Time3-7 business days
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Their engineering team helped us find a pin-compatible alternative when our original MCU went EOL.

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CTO, AutoDrive Systems, Italy