0402 10 nF MLCC Design Guide for High-Speed Decoupling

Bottom Line: Use a 10 nF 0402 X7R MLCC such as CL05B103KB5NNNC when the local bypass network must suppress high-frequency edges above the range where a 100 nF capacitor is still low impedance. Place the capacitor within 1-2 mm of the IC power pin, connect it with two short vias or a via-in-pad process, and pair it with 100 nF and 1 uF values so the power distribution network covers roughly 1 MHz to 500 MHz. Treat the package inductance, DC bias, and mounting geometry as design variables, not purchasing details.

Start With The Frequency Band The 10 nF Capacitor Must Control

A 10 nF MLCC is most useful when it is assigned to a specific high-frequency band instead of being scattered around a board by habit. In a typical digital or mixed-signal board, bulk capacitance handles load steps below a few hundred kilohertz, 1 uF and 100 nF capacitors support the mid-band, and a 10 nF 0402 part damps the upper band created by fast CMOS edges, clock buffers, ADC references, and small logic gates.

The key parameter is the capacitor self-resonant frequency. A simplified estimate is f = 1 / (2π sqrt(LC)), where C is capacitance and L is the mounted loop inductance. With 10 nF and an effective loop inductance near 0.5 nH, resonance is around 71 MHz; with 1.0 nH it falls near 50 MHz. That is why the same capacitor can behave differently on a tight four-layer PCB and a long two-layer layout.

For CL05B103KB5NNNC, the 0402 body and 50 V X7R dielectric make it useful near fast local nodes, but the board layout still dominates above resonance. A common mistake is to compare only nominal capacitance and voltage rating, then route the part through a long dogbone. The extra 2-3 nH can move the useful frequency band down by more than half and leave the IC pin exposed to ringing.

A practical rule is to define the target problem first. If the issue is a 200 MHz clock harmonic, a small 10 nF part near the pin makes sense. If the issue is a 20 us load transient from a radio or processor rail, a 10 nF capacitor is too small to be the primary energy source, and the design should prioritize 1 uF to 22 uF capacitors such as CL05A105KA5NQNC or larger package parts.

Control Loop Inductance Before Adding More Capacitors

Loop inductance usually decides whether a 0402 bypass capacitor works. The effective path is not the capacitor alone; it includes the pad, solder joint, trace segment, via barrel, power plane spreading path, and ground return. Every millimeter of narrow trace can add roughly 0.5-1 nH, which is large compared with the mounted inductance target for high-frequency decoupling.

Place the 10 nF MLCC on the same side as the IC when assembly rules allow it. The preferred layout is IC power pin to capacitor pad to via pair into the planes, with the ground via directly beside the ground-side pad. If the capacitor must sit on the back side, keep the via pair under or adjacent to the IC pins and avoid sending current through a long surface trace before it reaches the capacitor.

A good four-layer stackup gives the capacitor a low-impedance return path because the power and ground planes are close together. A two-layer board can still work, but it needs a wide local ground pour and very short routing. For a 0402 MLCC, a narrow 6 mil trace that runs 8 mm before reaching a via can make the part behave more like a small resonant antenna than a bypass component.

Do not solve a bad layout by adding ten identical 10 nF capacitors in a row. Identical parts share the same resonance and can produce anti-resonance peaks when mixed poorly with 100 nF and 1 uF values. Use one or two well-placed capacitors at the noisy pins first, then simulate or measure the PDN impedance if the rail feeds a high-speed ADC, FPGA bank, or RF transceiver.

Account For DC Bias, Tolerance, And Temperature

The installed capacitance of an MLCC is lower than the value printed in the catalog. X7R and X5R dielectrics lose capacitance under DC bias; the amount depends on case size, dielectric thickness, voltage rating, and manufacturer design. A 10 nF 50 V 0402 part usually has more DC-bias margin at 3.3 V or 5 V than a high-density 6.3 V part, but it still needs margin in the impedance budget.

Tolerance matters less for broadband bypassing than placement and ESL, but it still affects resonance. The ±10% value of CL05B103KB5NNNC means a board with many rails can have measurable unit-to-unit impedance variation. For a crystal oscillator load network or a filter pole, that same tolerance may be unacceptable, and a C0G part such as CL05C220JB5NNNC is a better fit even at lower capacitance.

Temperature also changes effective capacitance. X7R is specified over -55 °C to +125 °C with a capacitance shift limit of ±15% under the EIA dielectric class definition. That is suitable for most industrial bypassing, but it is not equivalent to C0G stability. When a 10 nF capacitor participates in a timing, RF, or precision filter path, check the dielectric class before reusing the decoupling BOM.

Voltage derating should be explicit. For a 3.3 V digital rail, a 50 V rated MLCC has generous bias headroom, while a 6.3 V 100 uF part may lose a large share of capacitance at the same rail. For high-frequency 10 nF use, a higher voltage rating is often an advantage because the part is physically robust enough to maintain capacitance without forcing a larger package.

Use case	Recommended parts	Why it works	Watch-outs
Fast logic or clock pin	CL05B103KB5NNNC plus CL05B104KO5NNNC	10 nF handles upper-band edges; 100 nF lowers local rail impedance	Avoid long shared traces between the two capacitors and the IC pin
Dense 3.3 V digital rail	cl05a104ka5nnnc plus CL05A105KA5NQNC	100 nF and 1 uF in 0402 keep placement compact	Confirm DC-bias loss on the 1 uF value at the actual rail voltage
Small analog or sensor rail	CL05B103KB5NNNC near the IC plus a local ferrite or resistor if isolation is needed	High-frequency shunting reduces digital feedthrough into the analog pin	Do not create a high-Q LC filter without damping

Common Pitfalls And Troubleshooting

The most common error is placing the capacitor by schematic grouping instead of current loop. A decoupling capacitor drawn beside the IC in the schematic is not automatically close on the PCB. If a rail still rings after assembly, inspect the physical loop area before changing capacitance.

A second error is using a single value everywhere. Ten 100 nF capacitors can create a neat BOM, but they may leave an impedance peak near the frequency where the package inductance takes over. Mix 10 nF, 100 nF, and 1 uF values only when each one has a placement role.

A third error is ignoring the return path. A capacitor connected to a fragmented ground pour has higher impedance than the same part connected to a continuous plane. If the board has slots, keep the decoupling loop on one side of the slot and never force the return current around a connector cutout.

A fourth error is replacing an X7R capacitor with an X5R or Y5V part without reviewing capacitance loss. The nominal value may match, but the installed capacitance and temperature behavior may not. For production substitutions, request the alternate datasheet and compare dielectric class, voltage rating, package size, and DC-bias curves before approving the change.

FAQ

Is a 10 nF capacitor still useful if every IC already has 100 nF decoupling?

Yes, a 10 nF 0402 capacitor can be useful when the problem frequency is above the effective range of the 100 nF part. With about 0.5-1 nH mounted loop inductance, a 10 nF MLCC resonates around 50-70 MHz, often closer to fast edge harmonics than a larger capacitor. It should be placed closer to the noisy pin than the 100 nF device.

Should the 10 nF capacitor be closer to the IC than the 100 nF capacitor?

Usually yes. The smallest capacitor assigned to the highest-frequency current should have the smallest loop area. Place the 10 nF part within about 1-2 mm of the power pin if the package and fanout permit it, then place the 100 nF and 1 uF capacitors just outside that loop. The exact order matters less when all capacitors use very short via pairs into solid planes.

Can CL05B103KB5NNNC replace a C0G 10 nF capacitor in filters?

Not without checking the circuit requirements. CL05B103KB5NNNC uses an X7R dielectric, which is appropriate for bypassing but changes with voltage and temperature. A precision filter, oscillator, or timing path may require C0G stability, where capacitance shift is much smaller. For bypassing a 3.3 V logic rail, X7R is usually the practical choice.

How should procurement handle shortages of this exact Samsung part?

Treat the substitute as an electrical and mechanical replacement, not just a capacitance match. Confirm 10 nF, 0402 size, voltage rating, X7R or better dielectric class, tolerance, operating temperature, and land pattern compatibility. For urgent builds, submit the approved alternates and quantity targets through FindMyChip RFQ so verified distributors can quote equivalent stock without changing the design intent.

Conclusion

A 10 nF 0402 MLCC earns its place when it is tied to high-frequency current control, tight placement, and a defined rail impedance target. CL05B103KB5NNNC is a practical choice for local high-speed decoupling, but the layout determines whether its low ESL can be used. Pair it with 100 nF and 1 uF capacitors, verify the return path, and review substitutes against dielectric, voltage, and package constraints before approving production changes.