SN74HC138PWG4 Texas Instruments Integrated Circuit (Small Outline Packages) In Stock
Texas Instruments SN74HC138PWG4 is a high-speed CMOS 3-to-8 line decoder/demultiplexer in a 16-pin TSSOP package. It features 3 enable inputs, propagation delay under 10 ns, and operates from 2 V to 6 V supply. Available from stock worldwide with fast shipping.
- Manufacturer
- Texas Instruments
- Package
- Small Outline Packages
- Pin Count
- 16
- Lifecycle
- OBSOLETE
- Datasheet
- SN74HC138PWG4 Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 3-to-8 line decoder with 3 enable inputs for cascadable multi-chip address decoding up to 64 outputs
- High-speed HC CMOS logic with propagation delay under 10 ns operating from 2 V to 6 V supply
- 16-pin TSSOP package with 50 pF load capacitance rating for compact high-density PCB layouts
- RoHS compliant (JESD-609 e4) with 4 mA output sink current suitable for driving LED and bus loads
Applications
SN74HC138PWG4 is used in microprocessor address decoding, memory chip-select generation, and LED matrix driving where 3 address lines must select one of 8 active-low outputs. Its three enable inputs allow straightforward cascading of multiple 74HC138 devices to decode 4, 5, or 6 address lines without additional logic. The TSSOP-16 package suits space-constrained PCBs in embedded controllers, FPGA expansion boards, and industrial automation logic circuits.
Specifications
| YTEOL | 0 |
| Additional Feature | 3 ENABLE INPUTS |
| Family | HC/UH |
| Input Conditioning | STANDARD |
| JESD-30 Code | R-PDSO-G16 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | 3-LINE TO 8-LINE DECODER |
| Max I(ol) | 0.004A |
| Number of Functions | 1 |
| Output Polarity | INVERTED |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | TSSOP16,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| Packing Method | TUBE |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 0.08mA |
| Prop. Delay@Nom-Sup | 45ns |
| Propagation Delay (tpd) | 225ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.65mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.60 |
Alternate & Equivalent Parts
Compatible alternatives and drop-in replacements for SN74HC138PWG4:
Frequently Asked Questions
How many outputs does SN74HC138PWG4 decode and at what supply voltage does it operate?
SN74HC138PWG4 decodes 3 binary address inputs into 8 active-low outputs, with 3 enable inputs for cascading. It operates from 2 V to 6 V supply with propagation delay under 10 ns at 5 V and 50 pF load. Output sink current is 4 mA, sufficient for driving standard CMOS logic loads and low-current LEDs directly.
How can multiple SN74HC138PWG4 devices be cascaded to decode a 6-bit address bus?
Cascading four SN74HC138PWG4 devices decodes a 6-bit address bus into 64 active-low chip-select signals. One master 74HC138 uses address bits A3-A5 to enable one of four slave 74HC138 devices, each decoding address bits A0-A2. The 3 enable inputs on each device include 2 active-low and 1 active-high pin, enabling straightforward glue-logic-free cascading in embedded memory systems.
What PCB package does SN74HC138PWG4 use and how does it compare to the DIP-16 variant?
SN74HC138PWG4 uses a 16-pin TSSOP package measuring approximately 4.4 mm wide with 0.65 mm pin pitch, consuming roughly 60% less board area than the DIP-16 version. The TSSOP suits high-density SMT assembly with reflow soldering, while DIP suits through-hole breadboard prototyping. Both variants share the same 3-to-8 decoder logic with identical 2 V to 6 V operating range.
When is SN74HC138PWG4 the right choice over an FPGA internal decoder for address demultiplexing?
SN74HC138PWG4 is preferred over FPGA internal logic when a simple 3-to-8 decode is needed outside the FPGA fabric, such as selecting off-chip memory devices or SPI peripherals. It adds decoding capability to microcontrollers with limited GPIO by converting 3 output pins into 8 chip-select lines, saving at least 5 GPIO pins at under 10 ns propagation delay per selection cycle.
Related Guides
How to Choose a BAS70 Schottky Diode for Signal Clamping: Selection Guide
A practical BAS70KFILM and BAS70-family Schottky diode selection guide for signal clamping, RF detection, leakage, and topology choices.
Jul 4, 2026
AMC1202DWVR Design Guide for Isolated Current Sensing
Practical AMC1202DWVR design guide covering shunt sizing, isolation layout, input filtering, ADC scaling, and sourcing choices.
Jul 4, 2026
1206 100 uF MLCC Design Guide for Compact Bulk Decoupling
Design guidance for applying CL31A107MQHNNNE and related 1206 MLCCs in compact bulk decoupling networks.
Jul 3, 2026
0402 10 nF MLCC Design Guide for High-Speed Decoupling
Practical design guidance for using CL05B103KB5NNNC and related 0402 MLCCs in high-speed decoupling networks.
Jul 3, 2026
Why Buy from FindMyChip
About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
In Stock · 24h Response · Worldwide Shipping
Response within 24 hours · Worldwide shipping
“Their engineering team helped us find a pin-compatible alternative when our original MCU went EOL.”