LTC6950IUHH#PBF Analog Devices Integrated Circuit (Quad Flat No-Lead) In Stock
The LTC6950IUHH#PBF is an ultralow-jitter integer-N PLL clock synthesizer and jitter cleaner with 5 programmable outputs in a 48-pin QFN package, delivering sub-100 fs RMS jitter for high-performance ADC clocking and communications infrastructure equipment.
- Manufacturer
- Analog Devices
- Package
- Quad Flat No-Lead
- Pin Count
- 48
- Lifecycle
- OBSOLETE
- Datasheet
- LTC6950IUHH#PBF Datasheet PDF
- Category
- Integrated Circuit
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- Ultralow phase noise integer-N PLL with sub-100 fs RMS additive jitter for precision ADC and DAC clocking up to 2.7 GHz
- 5 independently programmable LVPECL/LVDS/CMOS output drivers with individual dividers and output delays for multi-clock distribution
- SPI-configurable output dividers from 1 to 1023 enabling flexible clock plan generation without external circuitry
Applications
The LTC6950IUHH#PBF is designed for high-speed data converter clocking in software-defined radio, test and measurement instruments, and 5G base station signal chains where ADC sample clock jitter directly degrades SNR. Its 5 synchronized outputs distribute coherent low-jitter clocks to multiple ADCs, DACs, and DSP devices simultaneously in wideband receiver architectures. The jitter cleaning function recovers a low-noise clock from a noisy reference, eliminating the need for a separate VCXO-based jitter attenuator stage.
Specifications
| Pbfree Code | No |
| Manufacturer Package Code | 05-08-1845 |
| YTEOL | 0 |
| Analog IC - Other Type | PLL FREQUENCY SYNTHESIZER |
| JESD-30 Code | R-PQCC-N48 |
| JESD-609 Code | e3 |
| Number of Functions | 1 |
| Package Body Material | PLASTIC/EPOXY |
| Package Shape | RECTANGULAR |
| Package Style | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE |
| Supply Voltage-Max (Vsup) | 3.45V |
| Supply Voltage-Min (Vsup) | 3.15V |
| Supply Voltage-Nom (Vsup) | 3.3V |
| Surface Mount | YES |
| Technology | CMOS |
| Terminal Finish | Matte Tin (Sn) - annealed |
| Terminal Form | NO LEAD |
| Terminal Pitch | 0.5mm |
| Terminal Position | QUAD |
| Package | Quad Flat No-Lead |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.01 |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
What is the additive phase noise floor of the LTC6950IUHH#PBF and how does this affect ADC dynamic range?
The LTC6950IUHH#PBF achieves additive RMS jitter below 100 fs integrated from 12 kHz to 20 MHz, which corresponds to SNR degradation of less than 0.1 dB for a 16-bit ADC sampling at 250 MSPS with a 100 MHz input signal. This makes it suitable for driving high-speed converters in radar receivers and spectrum analyzers where the clock jitter budget must stay below 150 fs total to maintain full-resolution performance.
How many output channels does the LTC6950IUHH#PBF provide and can they be independently divided to different frequencies?
The LTC6950IUHH#PBF provides 5 independently configurable output channels, each with its own integer divider selectable from 1 to 1023 and an individual output delay adjustment. This allows a single device to simultaneously supply a 245.76 MHz ADC sample clock, a 122.88 MHz FPGA interface clock, and a 30.72 MHz baseband reference from one 3.932 GHz VCO, simplifying the clock tree in a 5G RRU design.
Which output signaling standards does the LTC6950IUHH#PBF support and what are their typical voltage swings?
Each of the 5 outputs on the LTC6950IUHH#PBF can be independently configured as LVPECL with an approximately 800 mV differential swing, LVDS with 350 mV differential swing, or CMOS with rail-to-rail swing up to 3.3 V. Mixed signaling modes allow one output to drive a 100 Ω LVPECL-terminated ADC clock input while another drives a CMOS-compatible FPGA reference pin without external level translators.
How does the LTC6950IUHH#PBF perform as a jitter cleaner on a noisy 10 MHz GPS reference input?
When locked to a noisy 10 MHz GPS disciplined oscillator reference, the LTC6950IUHH#PBF's PLL loop filter bandwidth can be set below 100 Hz to strongly attenuate reference spurs and phase noise above the loop bandwidth, transferring the VCO's inherent sub-100 fs close-in noise profile to the outputs. The result is a jitter-cleaned output with integrated RMS jitter below 200 fs from 10 Hz to 20 MHz, compared to over 1 ps RMS if the noisy reference were divided and used directly.
For a 5G mMIMO antenna unit, how does the LTC6950IUHH#PBF reduce clock distribution board area versus discrete PLL plus buffer solutions?
The LTC6950IUHH#PBF integrates the PLL core, VCO, and 5 fanout output drivers in a single 48-pin QFN package measuring 7 mm × 7 mm, replacing a discrete solution of a PLL chip plus a dedicated 5-output clock buffer that would occupy approximately 150 mm² combined. The single-chip integration also eliminates the 50 Ω transmission line between a separate PLL and buffer, reducing insertion loss and board-level jitter degradation in a compact mMIMO radio unit PCB.
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