CD74HC137E Texas Instruments Integrated Circuit (Dual-In-Line Packages) In Stock
CD74HC137E is a high-speed CMOS 3-line to 8-line decoder/demultiplexer with address latches, 3 enable inputs, and inverting outputs, operating from 2 V to 6 V. It drives 50 pF loads with 5.2 mA output sink current in a 16-pin PDIP through-hole package. Available from Texas Instruments with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Dual-In-Line Packages
- Pin Count
- 16
- Lifecycle
- ACTIVE
- Datasheet
- CD74HC137E Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.2842(MOQ 250)
- Temp Range
- -55.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- Integrated address latch allows the 3-bit input address to be captured on the fly, enabling glitch-free output decoding when address lines change
- 3 active-low enable inputs with inverting outputs provide flexible chip-select and bus-control logic without additional external gates
- Wide supply range of 2 V to 6 V makes CD74HC137E compatible with both 3.3 V and 5 V logic systems
- High-speed CMOS HC family ensures propagation delays well below 20 ns at 5 V, supporting address decoding at bus frequencies up to 50 MHz
Applications
CD74HC137E is used in memory and peripheral address decoding in microprocessor-based systems, where its 1-of-8 output selection maps a 3-bit CPU address field to up to 8 chip-select lines for RAM banks, ROM, or I/O devices. The integrated address latch allows the device to hold a stable decoded output while the address bus is multiplexed with data, simplifying interface logic in 8051 and Z80-style bus architectures. It also serves as a 1-of-8 demultiplexer in data distribution circuits, relay-driver select logic, and LED segment-control boards requiring inverting drive.
Specifications
| Pbfree Code | Yes |
| YTEOL | 15 |
| Additional Feature | ADDRESS LATCHES; 3 ENABLE INPUTS |
| Family | HC/UH |
| Input Conditioning | LATCHED |
| JESD-30 Code | R-PDIP-T16 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | 3-LINE TO 8-LINE DECODER |
| Max I(ol) | 0.0052A |
| Number of Bits | 8 |
| Number of Functions | 1 |
| Output Polarity | INVERTED |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | DIP16,.3 |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE |
| Packing Method | TUBE |
| Power Supply Current-Max (ICC) | 0.16mA |
| Prop. Delay@Nom-Sup | 36ns |
| Propagation Delay (tpd) | 270ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Supply Voltage-Nom (Vsup) | 4.5V |
| Surface Mount | NO |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| ## CD74HC137E Alternates Showing results | Image |
| Package | Dual-In-Line Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.90 |
| Country of Origin | Malaysia, Mexico |
Alternate & Equivalent Parts
Compatible alternatives and drop-in replacements for CD74HC137E:
Frequently Asked Questions
How does the address latch in CD74HC137E prevent glitches during address-bus transitions in a microprocessor system?
When the latch-enable (LE) input is driven low, CD74HC137E captures the 3-bit address A0–A2 into its internal latches and holds the decoded output stable even while the address bus switches to new values. This prevents false chip-selects caused by glitches during the 10 to 15 ns address setup time typical of 8-bit bus architectures, eliminating the need for external D-flip-flops or transparent latches that would otherwise add 1 to 2 extra ICs to the design.
Can CD74HC137E interface directly between a 3.3 V microcontroller and 5 V peripheral chip-select lines?
CD74HC137E operates from 2 V to 6 V, so it can be powered from 5 V to drive 5 V chip-select lines while accepting 3.3 V logic-high inputs (minimum VIH of approximately 3.5 V at 5 V supply). In practice, a 3.3 V input to a 5 V-powered CD74HC137E may fall in the indeterminate region for some units, so a level-shifter or powering the device from 3.3 V with VCC-matched peripherals is safer. At a 3.3 V supply it drives 3.3 V outputs cleanly with a 5.2 mA sink current.
What is the maximum output sink current of CD74HC137E and how does that constrain the loads it can drive?
CD74HC137E's maximum output sink current is 5.2 mA (I_OL) per output pin. This is sufficient to drive a single low-power CMOS input (which requires less than 1 µA) or a 330-ohm resistor to a 1.8 V LED forward voltage from a 5 V rail, but it cannot directly drive a standard TTL load requiring 8 mA without external buffer transistors. When driving memory chip-select pins with typical 10 pF input capacitance, the 5.2 mA current and 50 pF load capacitance spec support switching transitions within 10 ns at 5 V.
How does CD74HC137E compare to the 74HC138 for address decoding, and when should each be chosen?
CD74HC137E includes an on-chip address latch that the 74HC138 lacks, making the 137 the right choice when the address bus is multiplexed with data lines (as in Intel 8051 ALE-style interfaces) and must be demultiplexed before decoding. The 74HC138 is simpler and slightly faster at about 7 ns propagation delay at 5 V versus the 137's latch path of roughly 10 to 15 ns, so for non-multiplexed buses with stable address inputs the 74HC138 is preferred. Both devices operate from 2 V to 6 V in 16-pin packages.
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About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 250+ | $0.4010 | $100.25 |
| 500+ | $0.3780 | $189.00 |
| 5000+ | $0.3360 | $1680.00 |
| 100000+ | $0.2842 | $28420.00 |
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