AD9695BCPZ-1300 Analog Devices Integrated Circuit (Quad Flat No-Lead) In Stock
AD9695BCPZ-1300 is a dual 14-bit, 1300 MSPS analog-to-digital converter from Analog Devices featuring a JESD204B high-speed serial output interface in a 64-pin CSP package. Delivers exceptional dynamic range for wideband RF digitization. Available worldwide with fast shipping and competitive pricing.
- Manufacturer
- Analog Devices
- Package
- Quad Flat No-Lead
- Pin Count
- 64
- Lifecycle
- ACTIVE
- Datasheet
- AD9695BCPZ-1300 Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $145.9792(MOQ 2)
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- Dual 14-bit ADC sampling at 1300 MSPS with JESD204B serial interface supporting up to 8 lanes for direct RF digitization
- Exceptional SNR performance of 61 dBFS at 1 GHz input frequency enabling wideband signal capture with high dynamic range
- Integrated wideband decimation filters and NCO for digital downconversion, reducing FPGA resource consumption in software-defined radio applications
Applications
AD9695BCPZ-1300 is designed for wideband RF receivers in electronic warfare, phased-array radar, and communications base station applications requiring simultaneous dual-channel digitization at 1300 MSPS. Its JESD204B interface simplifies board routing to FPGAs and digital signal processors handling 1 GHz instantaneous bandwidth. The device also suits multi-carrier test and measurement instruments where high spurious-free dynamic range is critical.
Specifications
| Pbfree Code | No |
| Manufacturer Package Code | CP-64-17 |
| Reach Compliance Code | Compliant |
| Date Of Intro | 2017-09-18 |
| YTEOL | 8.5 |
| Analog Input Voltage-Max | 2.04V |
| Analog Input Voltage-Min | -2.04 V |
| Converter Type | ADC, PROPRIETARY METHOD |
| JESD-30 Code | S-XQCC-N64 |
| Linearity Error-Max (EL) | 0.0305% |
| Number of Analog In Channels | 2 |
| Number of Bits | 14 |
| Number of Functions | 1 |
| Output Bit Code | OFFSET BINARY, 2S COMPLEMENT BINARY |
| Output Format | SERIAL |
| Package Body Material | UNSPECIFIED |
| Package Equivalence Code | LCC64,.35SQ,20 |
| Package Shape | SQUARE |
| Package Style | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE |
| Peak Reflow Temperature (Cel) | 260 |
| Sample Rate | 1300MHz |
| Sample and Hold / Track and Hold | SAMPLE |
| Supply Voltage-Nom | 0.95V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Form | NO LEAD |
| Terminal Pitch | 0.5mm |
| Terminal Position | QUAD |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Quad Flat No-Lead |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 3 |
| ECCN | 3A001.A.5.A.4 |
| HTS Code | 8542.39.00.01 |
| Country of Origin | South Korea |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
What sampling rate and resolution does AD9695BCPZ-1300 provide for wideband RF digitization?
AD9695BCPZ-1300 samples at 1300 MSPS with 14-bit resolution on two simultaneous channels, providing an instantaneous analog bandwidth of approximately 650 MHz per channel. This allows direct RF digitization of L-band and S-band signals from 0.5 GHz to 1.3 GHz, eliminating the need for a separate analog downconversion stage in many radar and EW receiver designs.
How does the JESD204B interface on AD9695BCPZ-1300 simplify FPGA connectivity in a phased-array radar?
JESD204B supports multi-lane serial links at up to 12.5 Gbps per lane; AD9695BCPZ-1300 configures up to 8 lanes to deliver combined 1300 MSPS × 14-bit × 2-channel data to an FPGA. This replaces a parallel LVDS bus that would require 56 signal lines, cutting PCB layer count by 4 layers and enabling subarray integration of 16 dual-channel ADC modules.
What dynamic range performance does AD9695BCPZ-1300 achieve, and why is it important for electronic warfare receivers?
AD9695BCPZ-1300 achieves 61 dBFS SNR at a 1 GHz analog input, with spurious-free dynamic range (SFDR) exceeding 75 dBc. EW receivers must detect weak signals in the presence of strong jamming—a 75 dBc SFDR means the ADC self-generated spurs remain 75 dB below a full-scale jammer tone, preventing false target generation and ensuring reliable threat identification across a 500 MHz instantaneous band.
Can AD9695BCPZ-1300 replace AD9694-1000 in an existing PCB design, and what changes are required?
AD9695BCPZ-1300 uses the same 64-pin CSP footprint as AD9694-1000 and is pin-compatible for power and signal connections. The main change is increasing the sample clock to 1300 MHz from 1000 MHz and updating JESD204B lane settings in firmware to handle the higher data rate. Supply voltages remain 1.3 V core and 3.3 V digital I/O, so no power-plane redesign is needed.
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About Analog Devices
Analog Devices (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing integrated circuits used in virtually all types of electronic equipment.
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| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 2+ | $162.8229 | $325.65 |
| 3+ | $145.9792 | $437.94 |
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