74LVC139D,112 Nexperia Integrated Circuit (Other) In Stock
Nexperia 74LVC139D,112 is a dual 2-to-4 line decoder and demultiplexer in a 16-pin SOIC package, operating from 1.65 V to 5.5 V with 24 mA output drive, suitable for address decoding and signal routing in digital logic designs.
- Manufacturer
- Nexperia
- Package
- Other
- Pin Count
- 16
- Lifecycle
- OBSOLETE
- Datasheet
- 74LVC139D,112 Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.1915(MOQ 11)
- Temp Range
- -40.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- Dual 2-to-4 line decoder/demultiplexer with independent enable inputs for each decoder section
- Wide supply voltage range from 1.65 V to 5.5 V for compatibility with 1.8 V, 2.5 V, 3.3 V, and 5 V logic systems
- 24 mA (I_ol) output drive capability supports bus driving and medium-load applications
- 50 pF load capacitance specification enables reliable operation at typical digital logic switching speeds
- LVC family guarantees TTL-compatible input thresholds and CMOS output levels for mixed-voltage interfacing
- 16-pin SOIC (SOT109-1) package enables compact PCB layout in automated SMT production
Applications
The 74LVC139D,112 is widely used in address decoding for memory and peripheral selection in microcontroller and microprocessor systems, as well as chip select generation in FPGA-based designs. Its dual decoder sections with independent enable inputs also make it effective for signal demultiplexing, data routing, and line expansion in digital logic circuits operating across mixed 1.8 V to 5 V supply environments.
Specifications
| Manufacturer Package Code | SOT109-1 |
| Date Of Intro | 1994-08-01 |
| YTEOL | 0 |
| Family | LVC/LCX/Z |
| Input Conditioning | STANDARD |
| JESD-30 Code | R-PDSO-G16 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | 2-LINE TO 4-LINE DECODER |
| Max I(ol) | 0.024A |
| Number of Functions | 2 |
| Output Polarity | INVERTED |
| Package Body Material | PLASTIC/EPOXY |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE |
| Packing Method | TUBE |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 100mA |
| Prop. Delay@Nom-Sup | 6.5ns |
| Propagation Delay (tpd) | 11.3ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 1.2V |
| Supply Voltage-Nom (Vsup) | 1.8V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | AUTOMOTIVE |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | GULL WING |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Other |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.60 |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
What supply voltage range does 74LVC139D,112 support, and which logic families can it interface with?
The 74LVC139D,112 operates from 1.65 V to 5.5 V, making it compatible with 1.8 V, 2.5 V, 3.3 V, and 5 V logic systems. TTL-compatible input thresholds and CMOS output levels allow direct interfacing with LVC, LVHC, LVCMOS, and 5 V TTL logic families without additional level translation.
How can the dual independent enable inputs on 74LVC139D,112 simplify chip select generation in microcontroller designs?
Each of the two decoder sections has its own active-low enable input, allowing independent control of each 2-to-4 decoder. In a microcontroller design, one section can generate 4 chip select signals from 2 address bits while the second section controls another peripheral bank, all within a single 16-pin device with 24 mA output drive.
What package does 74LVC139D,112 use, and how does it affect PCB routing for address decode circuits?
The 74LVC139D,112 is packaged in a 16-pin SOIC (SOT109-1), a widely supported surface mount package that fits standard SMT footprints. The 16-pin layout with 1.27 mm pitch provides adequate pin spacing for routing 8 decoded output lines plus 2 select inputs and 2 enable lines without requiring fine-pitch PCB design rules.
How does 74LVC139D,112 compare to 74HC139 for 3.3 V digital systems?
The 74LVC139D,112 is preferred over 74HC139 for 3.3 V systems because LVC logic is optimized for low-voltage operation down to 1.65 V with faster propagation delays at reduced supply. The 74HC139 operates from 2 V to 6 V but is not specified for 1.8 V rails, while the LVC variant also accepts 5 V-tolerant inputs, making it safer in mixed-voltage 3.3 V and 5 V designs.
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About Nexperia
Nexperia is a leading electronic component manufacturer. FindMyChip sources Nexperia ICs directly from authorized China distributors, offering competitive pricing and reliable stock.
| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 11+ | $0.4896 | $5.39 |
| 1000+ | $0.3589 | $358.90 |
| 1534+ | $0.1915 | $293.76 |
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