7132LA55C IDT Integrated Circuit (Ceramic Dual-In-Line Packages) In Stock
The 7132 is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7142 "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535
- Manufacturer
- IDT
- Package
- Ceramic Dual-In-Line Packages
- Pin Count
- 48
- Lifecycle
- OBSOLETE
- Datasheet
- 7132LA55C Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- ?°C to 70.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- Integrated Circuit from IDT for production electronic assemblies
- Ceramic Dual-In-Line Packages package with 48 pins for PCB footprint planning
- Datasheet context includes 8-bit for engineering cross-checks
- Manufacturer or distributor datasheet URL available for technical verification
- Suitable for embedded systems, industrial electronics, communication equipment applications
Applications
7132LA55C is commonly used in embedded systems, industrial electronics, communication equipment, test fixtures, and production BOM sourcing where designers need dependable integrated circuit behavior and manufacturer-traceable sourcing. It is appropriate for production BOM builds, repair demand, and alternate qualification workflows that compare package fit, lifecycle status, and parameters such as 48 pins.
Specifications
| Pbfree Code | No |
| Manufacturer Package Code | SB48 |
| YTEOL | 0 |
| Access Time-Max | 55ns |
| Additional Feature | AUTOMATIC POWER-DOWN; BATTERY BACKUP |
| I/O Type | COMMON |
| JESD-30 Code | R-CDIP-T48 |
| JESD-609 Code | e0 |
| Memory Density | 16384bit |
| Memory IC Type | MULTI-PORT SRAM |
| Memory Width | 8 |
| Number of Functions | 1 |
| Number of Ports | 2 |
| Number of Words | 2048words |
| Number of Words Code | 2000 |
| Operating Mode | ASYNCHRONOUS |
| Organization | 2KX8 |
| Output Characteristics | 3-STATE |
| Package Body Material | CERAMIC, METAL-SEALED COFIRED |
| Package Equivalence Code | DIP48,.6 |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE |
| Parallel/Serial | PARALLEL |
| Peak Reflow Temperature (Cel) | 240 |
| Qualification Status | Not Qualified |
| Standby Current-Max | 0.0015A |
| Standby Voltage-Min | 2V |
| Supply Current-Max | 0.11mA |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | NO |
| Technology | CMOS |
| Temperature Grade | COMMERCIAL |
| Terminal Finish | TIN LEAD |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| Package | Ceramic Dual-In-Line Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.32.00.41 |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
Which design use cases are a practical fit for 7132LA55C?
7132LA55C is a Integrated Circuit from IDT suited to embedded systems, industrial electronics, communication equipment, test fixtures, and production BOM sourcing. The 48 pins detail helps engineers confirm schematic fit, interface allocation, and sourcing suitability before BOM approval.
How should engineers check package compatibility for 7132LA55C during layout review?
Use the Ceramic Dual-In-Line Packages package information together with 48 pins when comparing footprints, assembly drawings, and mating or socket constraints. This reduces layout risk before prototype or production purchasing.
What should procurement keep aligned when cross-referencing 7132LA55C against alternates?
Cross-reference checks should preserve the manufacturer, Integrated Circuit function, package style, lifecycle status, and at least one key parameter such as 8-bit. Matching these details lowers substitution risk across 1 approved BOM.
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