IDT

IDT70V3599S133BCGI is a 4.5 Mb multi-port SRAM with 36-bit wide data bus and 133 MHz clock frequency by IDT. Key specs: 256-ball BGA package (S-PBGA-B256), 15 ns maximum access time, pipelined and flow-through architecture. Available in stock with worldwide shipping.

The 74FST6800 Bus switch performs the function of connecting or isolating two ports without providing any inherent current sink or source capability. This device connecs input and output ports through an n-channel FET and has hot insertion capability. The low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero. The FST6800 provides a 10-Bit TTL-compatible interface. The 74FST6800 operates at -40C to +85C

The 74FST6800 Bus switch performs the function of connecting or isolating two ports without providing any inherent current sink or source capability. This device connecs input and output ports through an n-channel FET and has hot insertion capability. The low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero. The FST6800 provides a 10-Bit TTL-compatible interface. The 74FST6800 operates at -40C to +85C

The 932SQ420 is an Intel CK420BQ main clock synthesizer for Romley-generation and newer Intel-based server platforms. The 932SQ420 is driven with a 25 MHz crystal for maximum performance. It generates CPU outputs of 100 or 133.33 MHz.

The 70T3509M is a high-speed 1024K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3509M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.

IDT9LP505-1 follows Intel CK505 Yellow Cover for 64-TSSOP device specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. IDT9LP505-1 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.

The 9DBL0242 2-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0242 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.For information regarding evaluation boards and material, please contact your local sales representative.

The 502 Loco™ is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 160 MHz. Stored in the chip's ROM is the ability to generate six different multiplicati

The 502 Loco™ is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 160 MHz. Stored in the chip's ROM is the ability to generate six different multiplicati

The 841602I is an optimized PCIe and sRIO clock generator and member of the family of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the 8416

The 831742I is a high-performance, differential HCSL clock/data multiplexer and fanout buffer. The device is designed for the multiplexing and fanout of high-frequency clock and data signals. The device has four differential, selectable clock/data inputs. The selected input signal is distributed to two low-skew differential HCSL outputs. Each input pair accepts HCSL, LVDS, LVPECL and SSTL levels. The 831742I is characterized to operate from a 3.3V power supply. Guaranteed input, output-to-output and part-to

The 843004I-156 is a 4 output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies. Using a 25MHz 18pF parallel resonant crystal, the 843004I-156 can generate 156.25MHz.The 843004I-156 uses IDT's 3RD generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843004I-156 is packaged in a small 24-pin TSSOP E-Pad package.

IDT 9DB104BFLF is a Integrated Circuit for industrial, consumer, communications, and maintenance electronics. It provides 28 pins in a Small Outline Packages, with RoHS and Pb-free sourcing details. From quote-based pricing, request stock for worldwide shipping.

The 5P49V5944 is a programmable clock generator intended for high performance consumer, networking, industrial,computing, and data-communications applications.Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is IDTs fifth generation of programmable clock technology (VersaClock® 5).The frequencies are generated from a single input reference clock.The input reference can be either a crystal or an LVCMOS reference clock.Two select pins allow

The 841608I is an optimized PCIe and sRIO clock generator and member of the family of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (<1ps rms) suitable for clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the 8416

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The FCT3805 is a 3.3 volt clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputsand complies with the output specifications in this document. The FCT3805 offers low capacitance inputs.The FCT3805 is designed for high speed clock distribution where signal quality and skew are critical. The FCT3

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si

The 72V02 is a 1K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

Use the download button to access the 553SDCGI schematic symbol, PCB footprint, and 3D model.

The 5PB1104 is a high-performance 1:4 LVCMOS clock buffer. It has best-in-class Additive Phase Jitter of 50 fsec RMS.The 5PB1104 also supports an Output Enable function. It is available in 8-pin DFN and TSSOP packages and can operate from a 1.8 V to 3.3 V supply.

The 71321 is a high-speed 2K x 8 Dual-Port Static RAM with internal interrupt logic for interprocessor communications. It is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 71421 "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low sta

The 74FCT3245 octal high-speed, low-power transceiver is ideal for asynchronous communication between two buses. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. The 74FCT3245 has series current limiting resistors that offer low ground bounce, minimal undershoot, and controlled output fall times reducing the need for external series terminating resistors. The 74FCT3245 operates at -40C to +85C

The 74FCT3245 octal high-speed, low-power transceiver is ideal for asynchronous communication between two buses. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. The 74FCT3245 has series current limiting resistors that offer low ground bounce, minimal undershoot, and controlled output fall times reducing the need for external series terminating resistors. The 74FCT3245 operates at -40C to +85C

The 74FCT3245 octal high-speed, low-power transceiver is ideal for asynchronous communication between two buses. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. The 74FCT3245 has series current limiting resistors that offer low ground bounce, minimal undershoot, and controlled output fall times reducing the need for external series terminating resistors. The 74FCT3245 operates at -40C to +85C

The 74FCT3245 octal high-speed, low-power transceiver is ideal for asynchronous communication between two buses. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. The 74FCT3245 has series current limiting resistors that offer low ground bounce, minimal undershoot, and controlled output fall times reducing the need for external series terminating resistors. The 74FCT3245 operates at -40C to +85C

The 74FCT3245 octal high-speed, low-power transceiver is ideal for asynchronous communication between two buses. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. The 74FCT3245 has series current limiting resistors that offer low ground bounce, minimal undershoot, and controlled output fall times reducing the need for external series terminating resistors. The 74FCT3245 operates at -40C to +85C

The 1339 serial real-time clock (RTC) is a low-power clock/date device with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially through an I2C bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicato

The 1339 serial real-time clock (RTC) is a low-power clock/date device with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially through an I2C bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicato

The IDT 5P49V5901 is low-power programmable clock generator with best-in-class jitter performance and design flexibility with universal outputs capable of generating any output frequency. The 5P49V5901 is intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is IDTs fifth generation of programmable clock technology (VersaClock 5).The frequ

The 8V97051 is a high performance Wideband RF Synthesizer / PLL optimized for use as the local oscillator (LO) in Multi-Carrier, Multi-mode FDD & TDD Base Station radio card. It is offered in a compact 5x5, 32-VFQFN package.The 8V97051 Wideband RF Synthesizer / PLL offers a default Fractional Mode with the option to use it with an Integer mode. It requires an external loop filter.The 8V97051 with integrated Voltage Controlled Oscillator (VCO) supports output frequencies from 34.375MHz to 4400MHz and maint

Use the download button to access the 74FCT38072SCMGI schematic symbol, PCB footprint, and 3D model.

The 874001I-05 is a high performance Jitter Attenuator designed for use in PCI Express®™ systems. In some PCI Express® systems, such as those found in desktop PCs, the PCI Express® clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874001I-05 has a bandwidth of 6MHz with <1dB peaking, easily me

The 5P49V5933 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using an I2C interface. This is IDT's fifth generation of programmable clock technology (VersaClock® 5). The 5P49V5933, by default, uses an integrated 25 MHz crystal as an input reference. It also has a redundant external clock input. A glitchless manual switchover

The 5V41067A is a 2:4 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 5V41067A selects between 1 of 2 differential HCSL inputs to fanout to 4 differential HCSL output pairs. The outputs can also be terminated to LVDS.

Use the download button to access the 551SCMGI schematic symbol, PCB footprint, and 3D model.

The 5P49V5907 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is Renesas' fifth generation of programmable clock technology (VersaClock® 5). The frequencies are generated from a single reference clock or crystal.Two select pins allow up to 4 different configurations to be programmed and accessible u

The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer. The 8S89832I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin

The 8S89833I is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer with Internal Termination. The 8S89833I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components. The device also

The 5P1105 is a programmable fanout buffer intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface.The outputs are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation. Two

The 5P49V5908 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is Renesas' fifth generation of programmable clock technology (VersaClock® 5). The frequencies are generated from a single reference clock or crystal.Two select pins allow up to 4 different configurations to be programmed and accessible u

The 5P1103 is a programmable fanout buffer intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface.The outputs are generated from a single reference clock. The input reference can be crystal, external single-ended or differential clock. The reference clock can come from one of the two redundant clock inputs and is selected by CLKSEL pin. A glitch

The IDT 5P49V5914 is low-power programmable clock generator with best-in-class jitter performance and design flexibility with universal outputs capable of generating any output frequency. The 5P49V5914 is intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is IDT’s fifth generation of programmable clock technology (VersaClock 5). The fre

The IDT 5P49V5913 is low-power programmable clock generator with best-in-class jitter performance and design flexibility with universal outputs capable of generating any output frequency. The 5P49V5913 is intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is IDT’s fifth generation of programmable clock technology (VersaClock 5). The fre