47C04-I/ST Microchip Integrated Circuit (Small Outline Packages) In Stock
The Microchip 47C04-I/ST is a 4 Kbit EEPROM plus SRAM combination memory device in an 8-pin TSSOP package with 400 ns maximum access time. It integrates non-volatile EEPROM and volatile SRAM in a single compact IC for flexible data storage needs. Available from authorized distributors with worldwide shipping.
- Manufacturer
- Microchip
- Package
- Small Outline Packages
- Pin Count
- 8
- Lifecycle
- ACTIVE
- Datasheet
- 47C04-I/ST Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.6200(MOQ 1)
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of 47C04-I/ST?
- 4096-bit combined EEPROM and SRAM architecture in a single 8-pin TSSOP-8 package reduces BOM count and board space compared to separate discrete memory devices
- 400 ns maximum access time enables reliable data read and write operations in microcontroller-based systems with standard bus timing requirements
- 8-bit memory word width with serial interface compatibility simplifies firmware integration into embedded designs using I2C or SPI communication protocols
What is 47C04-I/ST used for?
The 47C04-I/ST is designed for embedded systems requiring both non-volatile parameter storage in EEPROM and fast scratch-pad SRAM within a single chip, such as sensor nodes, industrial control modules, and consumer electronics with limited PCB space. The 4 Kbit density is well matched to storing calibration data, configuration tables, and small runtime variables in microcontroller companion circuits. The compact TSSOP-8 footprint supports high-density PCB layouts common in IoT edge devices and wearable electronics.
What are the specifications of 47C04-I/ST?
| Manufacturer Package Code | TSSOP-8 |
| Date Of Intro | 2016-10-10 |
| YTEOL | 19 |
| Access Time-Max | 400ns |
| JESD-30 Code | R-PDSO-G8 |
| JESD-609 Code | e3 |
| Memory Density | 4096bit |
| Memory IC Type | MEMORY CIRCUIT |
| Memory Width | 8 |
| Mixed Memory Type | EEPROM+SRAM |
| Number of Functions | 1 |
| Number of Ports | 1 |
| Number of Words | 512words |
| Number of Words Code | 512 |
| Operating Mode | SYNCHRONOUS |
| Organization | 512X8 |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | TSSOP8,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.65mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.32.00.51 |
| Country of Origin | Philippines, Thailand |
Where can I find the 47C04-I/ST datasheet?
47C04-I/ST Datasheet DownloadOfficial datasheet from Microchip
What are equivalent replacements for 47C04-I/ST?
Compatible alternatives and drop-in replacements for 47C04-I/ST:
Microchip Technology Inc 4kbit SRAM with EEPROM backup, 4.5-5.5V
Frequently Asked Questions
What memory density and organization does the 47C04-I/ST offer for embedded data storage?
The 47C04-I/ST provides 4096 bits of combined EEPROM and SRAM storage organized in an 8-bit wide word format. This gives designers access to 512 bytes of addressable memory split between non-volatile EEPROM for configuration or calibration data and volatile SRAM for temporary runtime variables, all within a single 8-pin TSSOP-8 package.
How does the 400 ns access time of the 47C04-I/ST affect microcontroller bus timing requirements?
With a maximum access time of 400 ns, the 47C04-I/ST is compatible with most 8-bit and 16-bit microcontrollers running at clock speeds up to approximately 2.5 MHz in asynchronous bus mode without additional wait states. Faster microcontrollers operating at higher frequencies may require one or more wait states to meet the 400 ns read cycle timing specification.
In what types of sensor or industrial applications does combining EEPROM and SRAM in the 47C04-I/ST eliminate extra components?
In sensor calibration modules and PLC parameter storage applications, designers typically need both non-volatile EEPROM to retain factory calibration coefficients across power cycles and volatile SRAM for temporary measurement buffers. The 47C04-I/ST combines both functions in a single 4 Kbit device, eliminating the need for two separate memory chips and reducing PCB area by at least 30% compared to discrete solutions.
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More from Microchip
| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 1+ | $0.8200 | $0.82 |
| 100+ | $0.7000 | $70.00 |
| 1000+ | $0.6700 | $670.00 |
| 5000+ | $0.6200 | $3100.00 |
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