47C04-E/ST Microchip Integrated Circuit (Small Outline Packages) In Stock
The 47C04-E/ST is a 4 Kbit EERAM device in TSSOP-8 package, combining SRAM speed with EEPROM non-volatile storage at 5.0 V. It auto-saves SRAM contents to EEPROM on power loss and provides 400 ns maximum access time for critical data retention applications.
- Manufacturer
- Microchip
- Package
- Small Outline Packages
- Pin Count
- 8
- Lifecycle
- ACTIVE
- Datasheet
- 47C04-E/ST Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.6800(MOQ 1)
- Temp Range
- -40.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of 47C04-E/ST?
- 4 Kbit (512 bytes) combined SRAM and EEPROM in one device
- Automatic SRAM-to-EEPROM data store on power loss detection
- 400 ns maximum SRAM access time for fast read/write cycles
- I2C serial interface simplifying host MCU connectivity
- TSSOP-8 package with minimal 8-pin footprint
- 5.0 V operating voltage for compatibility with standard logic systems
What is 47C04-E/ST used for?
The 47C04-E/ST is used in embedded systems requiring fast SRAM access combined with non-volatile data retention, such as energy meters, industrial controllers, and IoT gateways that must preserve critical runtime variables during unexpected power interruptions. Its automatic store-on-power-loss feature eliminates the need for complex firmware backup routines or external supercapacitors. The I2C interface and 8-pin TSSOP footprint simplify integration alongside microcontrollers in compact PCB designs.
What are the specifications of 47C04-E/ST?
| Manufacturer Package Code | TSSOP-8 |
| Date Of Intro | 2016-10-10 |
| YTEOL | 19 |
| Access Time-Max | 400ns |
| JESD-30 Code | R-PDSO-G8 |
| JESD-609 Code | e3 |
| Memory Density | 4096bit |
| Memory IC Type | MEMORY CIRCUIT |
| Memory Width | 8 |
| Mixed Memory Type | EEPROM+SRAM |
| Number of Functions | 1 |
| Number of Ports | 1 |
| Number of Words | 512words |
| Number of Words Code | 512 |
| Operating Mode | SYNCHRONOUS |
| Organization | 512X8 |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | TSSOP8,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | AUTOMOTIVE |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.65mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.32.00.51 |
| Country of Origin | Philippines, Thailand |
Where can I find the 47C04-E/ST datasheet?
47C04-E/ST Datasheet DownloadOfficial datasheet from Microchip
What are equivalent replacements for 47C04-E/ST?
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
How does 47C04-E/ST automatically protect data during a power failure without firmware intervention?
The 47C04-E/ST monitors its VCC supply and, when a drop below the brownout threshold is detected, autonomously transfers all 512 bytes of SRAM contents to the internal EEPROM shadow array within the energy stored in bypass capacitors. On the next power-up, data is automatically restored from EEPROM to SRAM within the 400 ns access time window, ensuring no firmware code is needed to handle the save or restore sequence.
At 400 ns maximum access time, how does 47C04-E/ST compare to serial EEPROM for time-sensitive data logging?
Traditional I2C EEPROM devices such as 24LC04 require write cycle times of 5 ms per byte due to internal programming, limiting burst write rates. The 47C04-E/ST delivers SRAM-speed 400 ns random access for all write and read operations from the host perspective, enabling data logging at rates exceeding 1,000 writes per second without wait-state management.
Which system designs benefit most from replacing a discrete SRAM plus EEPROM combination with a single 47C04-E/ST?
Designs using a separate serial SRAM for speed and a separate serial EEPROM for non-volatile backup require two I2C addresses, two bypass capacitor networks, and two TSSOP or SOIC packages. Replacing both with the 47C04-E/ST saves at least 8 PCB components, reduces BOM cost, and consolidates 512 bytes of fast-access non-volatile storage into a single 8-pin TSSOP device.
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More from Microchip
| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 1+ | $0.8900 | $0.89 |
| 10+ | $0.8830 | $8.83 |
| 100+ | $0.7800 | $78.00 |
| 1000+ | $0.7200 | $720.00 |
| 5000+ | $0.6800 | $3400.00 |
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