24LC64-I/SM Microchip Integrated Circuit (Small Outline Packages) In Stock
Microchip 24LC64-I/SM is a 64-Kbit (8K × 8) I2C serial EEPROM operating from 2.5 V to 5.5 V in an SOIJ-8 surface-mount package. It supports a 400 kHz I2C bus clock with 200-year data retention and 1,000,000 write-erase cycles. Available in stock worldwide with fast shipping from authorized distributors.
- Manufacturer
- Microchip
- Package
- Small Outline Packages
- Pin Count
- 8
- Lifecycle
- ACTIVE
- Datasheet
- 24LC64-I/SM Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.2900(MOQ 1)
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 400 kHz I2C fast-mode interface allows rapid byte and page writes for configuration storage in embedded systems
- 1,000,000 write/erase cycle endurance combined with 200-year minimum data retention ensures long-term reliability in data logging and calibration storage
- 8-byte page write buffer reduces write latency in sequential data storage operations compared to single-byte write mode
Applications
The 24LC64-I/SM is widely used for storing calibration data, configuration parameters, and user settings in industrial instruments, medical devices, and consumer electronics. Its 64-Kbit capacity and I2C interface make it a compact companion to microcontrollers such as PIC, AVR, and STM32 families for persistent non-volatile storage. Designers also use it in smart meters, HVAC controllers, and IoT gateway boards where compact SOIJ-8 footprint and low-power standby are essential.
Specifications
| Pbfree Code | Yes |
| Manufacturer Package Code | SOIJ-8 |
| Factory Lead Time | 23Weeks |
| YTEOL | 8 |
| Clock Frequency-Max (fCLK) | 0.4MHz |
| Data Retention Time-Min | 200 |
| Endurance | 1000000 Write/Erase Cycles |
| I2C Control Byte | 1010DDDR |
| JESD-30 Code | R-PDSO-J8 |
| JESD-609 Code | e3 |
| Memory Density | 65536bit |
| Memory IC Type | EEPROM |
| Memory Width | 8 |
| Number of Functions | 1 |
| Number of Ports | 1 |
| Number of Words | 8192words |
| Number of Words Code | 8000 |
| Operating Mode | SYNCHRONOUS |
| Organization | 8KX8 |
| Output Characteristics | OPEN-DRAIN |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | SOP8,.3 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE |
| Parallel/Serial | SERIAL |
| Peak Reflow Temperature (Cel) | 260 |
| Programming Voltage | 4.5V |
| Qualification Status | Not Qualified |
| Serial Bus Type | I2C |
| Standby Current-Max | 0.000001A |
| Supply Current-Max | 0.003mA |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2.5V |
| Supply Voltage-Nom (Vsup) | 4.5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Form | J BEND |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Write Cycle Time-Max (tWC) | 5ms |
| Write Protection | HARDWARE |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.32.00.51 |
| Country of Origin | Thailand |
Alternate & Equivalent Parts
Compatible alternatives and drop-in replacements for 24LC64-I/SM:
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Frequently Asked Questions
What is the maximum I2C clock frequency supported by the 24LC64-I/SM?
The 24LC64-I/SM supports a 400 kHz I2C fast-mode clock, enabling efficient sequential byte and page writes for configuration storage applications while operating from a 2.5 V to 5.5 V supply across the industrial -40°C to 85°C temperature range.
How long can data be reliably retained in the 24LC64-I/SM, and how many write cycles does it endure?
The device guarantees a minimum data retention of 200 years and an endurance of 1,000,000 write/erase cycles, making it suitable for frequent-update applications such as event counters, odometers, and calibration coefficient storage in field-deployed instruments.
What is the memory organization and page write size of the 24LC64-I/SM?
The 24LC64-I/SM organizes its 64 Kbits as 8,192 bytes and supports a 32-byte page write buffer, allowing up to 32 bytes to be written in a single I2C transaction and significantly reducing write time compared to single-byte sequential writes.
How do the address pins on the 24LC64-I/SM allow multiple devices to share a single I2C bus?
Three hardware address pins (A0, A1, A2) can be tied high or low to set the 3 least significant bits of the device address, enabling up to 8 24LC64 devices on one I2C bus and providing up to 512 Kbits of total addressable non-volatile storage on a shared 2-wire interface.
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| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 1+ | $0.5380 | $0.54 |
| 10+ | $0.5030 | $5.03 |
| 12+ | $0.4772 | $5.73 |
| 300+ | $0.3050 | $91.50 |
| 750+ | $0.3000 | $225.00 |
| 1500+ | $0.2900 | $435.00 |
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