24LC64T-I/SN Microchip Integrated Circuit (Small Outline Packages) In Stock
The 24LC64T-I/SN is a 64 Kbit (8K × 8) I2C serial EEPROM operating from 2.5 V to 5.5 V with a 400 kHz clock and 1,000,000-cycle write endurance. It delivers reliable non-volatile storage in a compact 8-pin SOIC package with 200-year data retention. Available from stock worldwide with fast shipping.
- Manufacturer
- Microchip
- Package
- Small Outline Packages
- Pin Count
- 8
- Lifecycle
- ACTIVE
- Datasheet
- 24LC64T-I/SN Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.2700(MOQ 1)
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 64 Kbit (8K × 8) I2C EEPROM with 400 kHz Fast mode and hardware write-protect pin for secure data management
- 1,000,000 write/erase cycle endurance and 200-year data retention for long-life embedded applications
- 2.5 V to 5.5 V supply range in an 8-pin SOIC package with page-write capability up to 32 bytes
Applications
The 24LC64T-I/SN is well suited for storing calibration data, configuration tables, and firmware parameters in industrial sensors, medical instruments, and consumer electronics. Its 400 kHz I2C interface allows up to 8 devices on a single bus using address pins A0–A2, simplifying multi-node data-logging systems. The wide 2.5 V to 5.5 V supply range and small 8-pin SOIC footprint ease integration into both 3.3 V and 5 V microcontroller designs.
Specifications
| Pbfree Code | Yes |
| Manufacturer Package Code | SOIC-8 |
| Factory Lead Time | 24Weeks |
| YTEOL | 8 |
| Clock Frequency-Max (fCLK) | 0.4MHz |
| Data Retention Time-Min | 200 |
| Endurance | 1000000 Write/Erase Cycles |
| I2C Control Byte | 1010DDDR |
| JESD-30 Code | R-PDSO-G8 |
| JESD-609 Code | e3 |
| Memory Density | 65536bit |
| Memory IC Type | EEPROM |
| Memory Width | 8 |
| Number of Functions | 1 |
| Number of Ports | 1 |
| Number of Words | 8192words |
| Number of Words Code | 8000 |
| Operating Mode | SYNCHRONOUS |
| Organization | 8KX8 |
| Output Characteristics | OPEN-DRAIN |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | SOP8,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE |
| Parallel/Serial | SERIAL |
| Peak Reflow Temperature (Cel) | 260 |
| Programming Voltage | 4.5V |
| Qualification Status | Not Qualified |
| Serial Bus Type | I2C |
| Standby Current-Max | 0.000001A |
| Supply Current-Max | 0.003mA |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2.5V |
| Supply Voltage-Nom (Vsup) | 4.5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Form | GULL WING |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Write Cycle Time-Max (tWC) | 5ms |
| Write Protection | HARDWARE |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.32.00.51 |
| Country of Origin | Mainland China, Philippines, Taiwan, Thailand |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
How many write cycles can the 24LC64T-I/SN endure before wear becomes a concern?
The 24LC64T-I/SN is rated for 1,000,000 write/erase cycles per byte location. At that point the cell may no longer retain data reliably. For high-frequency write applications, designers should implement wear-leveling across the 8,192 available byte addresses to maximize device lifespan, and note the 200-year data retention specification under normal conditions.
How many 24LC64T-I/SN devices can share a single I2C bus, and how is addressing configured?
Up to 8 devices can share a single I2C bus using the 3 hardware address pins A0, A1, and A2 to set unique addresses via the I2C control byte format 1010DDDR. The bus operates at up to 400 kHz in Fast mode, and each device provides 8 KB of storage, giving a maximum shared capacity of 64 KB on one bus segment.
What page-write size does the 24LC64T-I/SN support, and how does it affect write latency?
The 24LC64T-I/SN supports page writes of up to 32 bytes per operation, substantially reducing the number of I2C transactions compared to byte-by-byte writes. After each page write, a self-timed internal programming cycle of up to 5 ms must complete before the next write begins, so firmware should poll the ACK bit or wait the specified tWR period.
Which supply voltages does the 24LC64T-I/SN support, making it compatible with modern 3.3 V microcontrollers?
The 24LC64T-I/SN operates from 2.5 V to 5.5 V, covering 3.3 V, 5 V, and even lower-voltage rails. At 2.5 V, all I2C timing and endurance specifications are maintained, making it directly compatible with low-power ARM Cortex-M and AVR microcontrollers without the need for level shifters in standard 3.3 V designs.
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| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 1+ | $0.5100 | $0.51 |
| 10+ | $0.3466 | $3.47 |
| 25+ | $0.3458 | $8.64 |
| 100+ | $0.3429 | $34.29 |
| 1000+ | $0.3410 | $341.00 |
| 3300+ | $0.2700 | $891.00 |
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