Integrated Circuit
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- 1Verify electrical specifications (voltage, current, frequency) match your design requirements.
- 2Check package footprint and thermal characteristics against your PCB layout constraints.
- 3Confirm lifecycle status and long-term availability for production designs.
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Integrated Circuit Guides & Articles
How to Choose 150141BS73100 for Wurth 3528 SMT LED Indicator Designs
Selection guide for 150141BS73100 and Wurth 3528 SMT LED variants covering color, drive current, package fit, optics, and sourcing.
Jul 9, 2026
How to Choose EEEFT1V101AP for SMD Aluminum Electrolytic Capacitor Designs
Selection guide for EEEFT1V101AP and related Panasonic EEE-FT SMD aluminum electrolytic capacitors covering voltage, ESR, lifetime, and sourcing.
Jul 9, 2026
How to Choose a Panasonic FT SMD Aluminum Electrolytic Capacitor for 35 V Control Rails
Selection guide for EEEFT1V101AP and related Panasonic FT/FK SMD aluminum electrolytic capacitors on 35 V and lower control rails.
Jul 8, 2026
EEEFK1E470P Design Guide for 24 V Control-Board Hold-Up
Design EEEFK1E470P into 12 V and 24 V control boards with correct voltage derating, ripple checks, layout, and sourcing alternatives.
Jul 8, 2026
All Integrated Circuit Components
Showing 1,901–1,950 of 76,414
Low Output Saturation Voltage: 130 mV (Typ) @ 4.0 mA; Single or Split Supply Operation; TTL and CMOS Compatible; Input Common Mode Voltage Range to Gnd; ESD Clamps on the Inputs Increase Reliability without Affecting Device Operation; Low Input Bias Current: 25 nA (Typ); Low Input Offset Current: +/- 5.0 nA (Typ)
SOIC-16
Two Disable Controls for Added Versatility; TTL Compatible - Will Drive One TTL Load Over Full Temperature Range; 3-State Outputs; Pin for Pin Replacement for MM80C97 and 340097; Supply Voltage Range = 3.0 Vdc to 18 Vdc; Pb-Free Packages are Available
Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range; Can Be Used to Replace the MC14584B or MC14069UB; Pin-for-Pin Replacement for CD40106B and MM74C14; Increased Hysteresis Voltage Over the MC14584B; Supply Voltage Range = 3.0 Vdc to 18 Vdc; Pb-Free Packages are Available*
Useful for Serial-to-Parallel Data Conversion; Pin-for-Pin Compatible with CD4094B; Data Latch; Input Diode Protection; Dual Outputs for Data Out on Both Positive and Negative Clock Transitions; Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range; Three-State Outputs; Pb-Free Packages are Available*
Outputs Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range; Double Diode Input Protection; Three-State Outputs with Common Enable; Supply Voltage Range = 3.0 Vdc to 18 Vdc; Pb-Free Packages are Available*
Outputs Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range; Double Diode Input Protection; Three-State Outputs with Common Enable; Supply Voltage Range = 3.0 Vdc to 18 Vdc; Pb-Free Packages are Available*
Use the download button to access the MC14042BDG schematic symbol, PCB footprint, and 3D model.
Synchronous Parallel Input/Serial Output (MC14014B); Full Static Operation; Double Diode Input Protection; "Q" Outputs from Sixth, Seventh, and Eighth Stages; MC14021B Pin-for-Pin Replacement for CD4021B; Synchronous Serial Input/Serial Output; Supply Voltage Range = 3.0 Vdc to 18 Vdc; Asynchronous Parallel Input/Serial Output (MC14021B); MC14014B Pin-for-Pin Replacement for CD4014B; Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range; Pb-Free Packa
Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range.; Logic Edge-Clocked Flip-Flop Design - Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive goingedge of the clock pulse.; Supply Voltage Range = 3.0 Vdc to 18 Vdc; Diode Protection on All Inputs; Pb-Free Packages are Available*
LEAD FREE, PLASTIC, DIP-16
Maximum Frequency > 3 Ghz Typical; 350ps Typical Propagation Delay; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available
Use the download button to access the MC10EP08DG schematic symbol, PCB footprint, and 3D model.
LEAD FREE, PLASTIC, TSSOP-8
ESD Protection: > 1 KV HBM, > 100 V MM; 475ps Propagation Delay; 2.8GHz Toggle Frequency; PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V; NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V; Internal Input Pulldown Resistors on D, CLK, S, and R; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; Metastability 125 ps (see App
2.0ns Typical Propagation Delay; PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with GND= 0 V; Maximum Frequency > 180 MHz; Flow Through Pinouts; Internal Pulldown Resistors; Differential LVPECL Inputs; 24 mA LVTTL Outputs; Q Output will default LOW with inputs open or at GND; ESD Protection: >1.5 KV HBM, >100 V MM; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxyge
<100ps Output-to-Output Skew; Flow Through Pinouts; ESD Protection: >4 KV HBM, >200 V MM; The 100 Series Contains Temperature Compensation; 350ps Typical Propagation Delay; LVPECL Operating Range: VCC= 3.15 V to 3.45 V with GND= 0 V; When Unused TTL Input is left Open, Q Output will Default High; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; Tr
Q Output will default LOW with inputs open or at GND; 24mA TTL outputs; Maximum Frequency > 275 MHz Typical; 1.1ns Typical Propagation Delay; Operating Range: VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0 V; VBB Output; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available
Operating Range V CC = 3.0V to 3.6V with GND = 0; Q Output will default HIGH with inputs open; 390ps Typical Propagation Delay; Maximum Frequency > 1 Ghz Typical; PNP TTL Inputs for Minimal Loading
SOIC-8
375 ps Typical Propagation Delays Maximum Frequency > 2 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Q Output will default LOW with inputs open or at VEE VBB Outputs Useful as Either 4:1 or 2:1 Multiplexer These Devices are Pb−Free and are RoHS Compliant
Use the download button to access the MC100EP56DWG schematic symbol, PCB footprint, and 3D model.
360 ps Typical Propagation Delays Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Separate and Common Select Q Output Will Default LOW with Inputs Open or at VEE VBB Outputs These Devices are Pb−Free and are
Maximum Frequency > 3 Ghz Typical; 350ps Typical Propagation Delay; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available
SOP-8
PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V; 350ps Typical Propagation Delay; NECL Mode Operating Range: VCC= 0 V with VEE= –3.0 V to –5.5 V; Q Output will default LOW with inputs open or at VEE; Maximum Frequency > 4 GHz Typical; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available
220 ps Propagation Delay; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; Maximum Frequency > 4 GHz Typical (See Graph); PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; Open Input Default State; Safety Clamp on Inputs; Q Output Will Default LOW with Inputs Open or at VEE; VBB Output
100 ps Device-to-Device Skew; 25 ps Within Device Skew; 400 ps Typical Propagation Delay; Maximum Frequency > 2 GHz Typical; PECL and HSTL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V; Open Input Default State; The 100 Series Contains Temperature Compensation
Use the download button to access the MC100EP140DG schematic symbol, PCB footprint, and 3D model.
Use the download button to access the MC100EP11DG schematic symbol, PCB footprint, and 3D model.
SOIC-8
ON Semiconductor MC100ELT20DG, Logic Level Translator, TTL to PECL, 4.75 → 5.25 V, 8-Pin SOIC
NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V; PECL Mode Operating Range: VCC= 4.2 V to 5.7 with VEE= 0 V; ESD Protection: > 1 KV HBM, > 100 V MM; 5ps Skew Between Outputs; 265ps Propagation Delay; Internal Input Pulldown Resistors; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; Transistor Count = 44 devices; Pb-Free Packages ar
4 X 4 MM, VQFN-24
Wide Operating Vcc Range; High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V; CMOS-Compatible Outputs: VOH > 0.8 VCC ; VOL < 0.1 VCC @Load; Power Down Protection Provided on Inputs and Outputs; Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available
Use the download button to access the MAX809JTRG schematic symbol and PCB footprint.
ON Semiconductor MAX810MTRG, Voltage Supervisor, 1.2 → 4.9 V, 3-Pin SOT-23
ON Semiconductor LV8761V-TLM-E, Full Bridge Motor Driver Bidirectional Motor, 36-Pin SSOP
High Speed: tPD = 3.5ns (Typ) at VCC = 5V; Low threshold Inputs, TTL compatible if Vcc= 5 V: VIL = 0.8V; VIH = 2.0V; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; CMOS-Compatible Outputs: VOH > 0.8VCC ; VOL < 0.1VCC @Load; Wide Operating Vcc Rang; Power Down Protection Provided on Inputs and Outputs; Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available
LP2951 also has Output Programmable from 1.25 V to 29 V; Requires Only a 1.0 mF Output Capacitor for Stability; Rated Output Current of 100 mA; Low Quiescent Current: 75 µA (Typ); Wide Input Range: Up to 30 V; Low Dropout 50 mV at 100 mA and 380 mV at 100 mA; LP2951 also has Error(bar) Output Signals an Out of Regulation Condition; Internal Current and Thermal Limiting; LP2951 also has Logic Level Shutdown Input; Extremely Tight Line and Load Regulation; 5.0 V, 3.3 V or 3.0 V +/- 0.5%
LP2951 also has Output Programmable from 1.25 V to 29 V; Requires Only a 1.0 mF Output Capacitor for Stability; Rated Output Current of 100 mA; Low Quiescent Current: 75 µA (Typ); Wide Input Range: Up to 30 V; Low Dropout 50 mV at 100 mA and 380 mV at 100 mA; LP2951 also has Error(bar) Output Signals an Out of Regulation Condition; Internal Current and Thermal Limiting; LP2951 also has Logic Level Shutdown Input; Extremely Tight Line and Load Regulation; 5.0 V, 3.3 V or 3.0 V +/- 0.5%
SOIC-8
LP2951 also has Output Programmable from 1.25 V to 29 V; Requires Only a 1.0 mF Output Capacitor for Stability; Rated Output Current of 100 mA; Low Quiescent Current: 75 µA (Typ); Wide Input Range: Up to 30 V; Low Dropout 50 mV at 100 mA and 380 mV at 100 mA; LP2951 also has Error(bar) Output Signals an Out of Regulation Condition; Internal Current and Thermal Limiting; LP2951 also has Logic Level Shutdown Input; Extremely Tight Line and Load Regulation; 5.0 V, 3.3 V or 3.0 V +/- 0.5%
SOIC-8
LP2951 also has Output Programmable from 1.25 V to 29 V; Requires Only a 1.0 mF Output Capacitor for Stability; Rated Output Current of 100 mA; Low Quiescent Current: 75 µA (Typ); Wide Input Range: Up to 30 V; Low Dropout 50 mV at 100 mA and 380 mV at 100 mA; LP2951 also has Error(bar) Output Signals an Out of Regulation Condition; Internal Current and Thermal Limiting; LP2951 also has Logic Level Shutdown Input; Extremely Tight Line and Load Regulation; 5.0 V, 3.3 V or 3.0 V +/- 0.5%
LP2951 also has Output Programmable from 1.25 V to 29 V; Requires Only a 1.0 mF Output Capacitor for Stability; Rated Output Current of 100 mA; Low Quiescent Current: 75 µA (Typ); Wide Input Range: Up to 30 V; Low Dropout 50 mV at 100 mA and 380 mV at 100 mA; LP2951 also has Error(bar) Output Signals an Out of Regulation Condition; Internal Current and Thermal Limiting; LP2951 also has Logic Level Shutdown Input; Extremely Tight Line and Load Regulation; 5.0 V, 3.3 V or 3.0 V +/- 0.5%
Use the download button to access the LP2951ACD-3.0G schematic symbol, PCB footprint, and 3D model.
Use the download button to access the LMV932DR2G schematic symbol, PCB footprint, and 3D model.
Operation from 2.7 V to 5.0 V Single-Sided Power Supply; No Output Crossover Distortion; Industrial temperature Range: -40C to +85C; Rail-to-Rail Output; Low Quiescent Current; No Output Phase-Reversal from Overdriven Input
Operation from 2.7 V to 5.0 V Single-Sided Power Supply; No Output Crossover Distortion; Industrial temperature Range: -40C to +85C; Rail-to-Rail Output; Low Quiescent Current; No Output Phase-Reversal from Overdriven Input
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