ON Semiconductor

Designed for 2.7 to 3.6V VCC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; LVTTL Compatible; 24mA Balanced Output Sink and Source Capability; Latchup Performance Exceeds 500mA; Pb-Free Packages are Available*

5V Tolerant Inputs - Interface Capability With 5V TTL Logic; ESD Performance: Human Body Model >2000V; Machine Model >200V; Latchup Performance Exceeds 500mA; Near Zero Static Supply Current (10µA) Substantially Reduces System Power Requirements; LVCMOS Compatible; Designed for 2.3 to 3.6V VCC Operation; 24mA Balanced Output Sink and Source Capability; LVTTL Compatible; Pb-Free Packages are Available*

5V Tolerant Inputs - Interface Capability With 5V TTL Logic; LVTTL Compatible; 24mA Balanced Output Sink and Source Capability; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; Designed for 2.3 V to 3.6 V VCC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; Latchup Performance Exceeds 500mA; LVCMOS Compatible; Pb-Free Packages are Available*

Output Drive Capability: 15 LSTTL Loads; TTL NMOS-Compatible Input Levels; Outputs Directly Interface to CMOS, NMOS, and TTL; Operating Voltage Range: 4.5 to 5.5 V; Low Input Current: 1 mA; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 112 FETs or 28 Equivalent Gates; Pb-Free Packages are Available

Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; ESD Performance: Human Body Model >2000V; Machine Model >200V; Designed for 2.3V to 3.6V VCC Operation; Latchup Performance Exceeds 500mA; LVTTL Compatible; LVCMOS Compatible; 24mA Balanced Output Sink and Source Capability; Pb-Free Packages are Available*

In Compliance with the Requirements Defined by JEDEC Standard No. 7A; TTL/NMOS-Compatible Input Levels; Chip Complexity: 72 FETs or 18 Equivalent Gates; Operating Voltage Range: 4.5 to 5.5 V; Output Drive Capability: 10 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS and TTL; Low Input Current: 1.0 mA; Pb-Free Packages are Available

LVCMOS Compatible; ESD Performance: Human Body Model >1500V; Machine Model >200V; 5 V Tolerant Inputs/Outputs; LVTTL Compatible; 24mA Output Sink Capability; Designed for 2.3 to 5.5 V VCC Operation; Latchup Performance Exceeds 500mA; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; Wired-OR, Wired-AND; Output Can Be Set Externally Without Affecting Speed or Device; Pb-Free Packages are Available*

Designed for 2.7 to 3.6V VCC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; LVTTL Compatible; 24mA Balanced Output Sink and Source Capability; Latchup Performance Exceeds 500mA; Pb-Free Packages are Available*

Output Drive Capability: 10 LSTTL Loads; High Noise Immunity Characteristic of CMOS Devices; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1 mA; Chip Complexity: 12 FETs or 3 Equivalent Gates; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator Configurations; Pb-Free Packages are Available

ESD Performance: Human Body Model >2000V; Machine Model >200V; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; 24mA Balanced Output Sink and Source Capability; Designed for 2.3 to 3.6V VCC Operation; LVCMOS Compatible; Latchup Performance Exceeds 500mA; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; LVTTL Compatible

Use the download button to access the MC74LCX02DG schematic symbol, PCB footprint, and 3D model.

Outputs Directly Interface to CMOS, NMOS, and TTL; Operating Voltage Range: 4.5 to 5.5 V; Low Input Current: 1.0 mA; Output Drive Capability: 15 LSTTL Loads; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Improvements over HCT374 - Improved Propagation Delays - 50% Lower Quiescent Power - Improved Input Noise and Latchup Immunity; TTL/NMOS-Compatible Input Levels; Chip Complexity: 276 FETs or 69 Equivalent Gates; Pb-Free Packages are Available*

Obsolete - Low Voltage CMOS Hex Inverter with Open Drain Outputs and 5V-Tolerant I/Os

Chip Complexity: 56 FETs or 14 Equivalent Gates; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1 mA; Operating Voltage Range: 2 to 6 V; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Output Drive Capability: 10 LSTTL Loads; Pb-Free Packages are Available

Output Drive Capability: 15 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS, and TTL; Operating Voltage Range: 4.5 to 5.5 V; Low Input Current: 1.0 uA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 328 FETs or 82 Equivalent Gates

Operating Voltage Range: 2.0 to 6.0 V; Output Drive Capability: 15 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1.0 mA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 328 FETs or 82 Equivalent Gates; Improvements over HC595 Improved Propagation Delays 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity; Pb-Free Packages are Available*

SOIC-16

Low Input Current: 10 mA; Chip Complexity: 234 FETs or 58.5 Equivalent Gates - Improved Propagation Delays - 50% Lower Quiescent Power; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Outputs Directly Interface to CMOS, NMOS and TTL; TTL/NMOS-Compatible Input Levels; Output Drive Capability: 15 LSTTL Loads; Operating Voltage Range: 4.5 to 5.5 V; These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at

SOP-16

Operating Voltage Range: 2.0 to 6.0 V; Output Drive Capability: 15 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1.0 mA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 328 FETs or 82 Equivalent Gates; Improvements over HC595 Improved Propagation Delays 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity; Pb-Free Packages are Available*

Low Crosstalk Between Switches; Fast Switching and Propagation Speeds; Chip Complexity: HC4051A - 184 FETs or 46 Equivalent Gates HC4052A - 168 FETs or 42 Equivalent Gates HC4053A - 156 FETs or 39 Equivalent Gates; Analog Power Supply Range (VCC - VEE ) = 2.0 to 12.0 V; In Compliance With the Requirements of JEDEC Standard No. 7A; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Diode Protection on All Inputs/Outputs; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; L

Operating Voltage Range: 2.0 to 6.0 V; Output Drive Capability: 15 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1.0 mA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 328 FETs or 82 Equivalent Gates; Improvements over HC595 Improved Propagation Delays 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity; Pb-Free Packages are Available*

Operating Voltage Range: 2.0 to 6.0 V; Output Drive Capability: 15 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1.0 mA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 328 FETs or 82 Equivalent Gates; Improvements over HC595 Improved Propagation Delays 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity; Pb-Free Packages are Available*

Outputs Directly Interface to CMOS, NMOS and TTL; +/- 10% Guaranteed Pulse Width Variation from Part to Part (Using the Same Test Jig); Output Pulse is Independent of the Trigger Pulse Width; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 145 FETs or 36 Equivalent Gates; Output Drive Capability: 10 LSTTL Loads; Operating Voltage Range: 3.0 to 6.0 V; High Noise Immunity Characteristic of CMOS Devices; Low Input Current: 1.0 mA; Unlimited Rise and Fall Times Allowed on

Improved Linearity of ON Resistance; Chip Complexity: 66 FETs or 16.5 Equivalent Gates; Fast Switching and Propagation Speeds; Logic-Level Translator for On/Off Control and Enable Inputs; Analog Power-Supply Voltage Range (VCC - VEE) = 2.0 to 12.0 Volts; High ON/OFF Output Voltage Ratio; Diode Protection on All Inputs/Outputs; Digital (Control) Power-Supply Voltage Range (VCC - GND) = 2.0 to 6.0 Volts, Independent of VEE; Pb-Free Packages are Available*

Low Input Current: 1 mA; Operating Voltage Range: 2 to 6 V; High Noise Immunity Characteristic of CMOS Devices; Chip Complexity: 526 FETs or 131.5 Equivalent Gates; Output Drive Capability: 15 LSTTL Loads; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Outputs Directly Interface to CMOS, NMOS, and TTL; Pb-Free Packages are Available

HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, DIP-16

Fast Switching and Propagation Speeds; High ON/OFF Output Voltage Ratio; Low Crosstalk Between Switches; Diode Protection on All Inputs/Outputs; Wide PowerSupply Voltage Range (VCC-GND) = 2.0 to 6.0 V; Analog Input Voltage Range (VCC-GND) = 0 to 6.0 V; Improved Linearity and Lower ON Resistance over Input Voltage; Low Noise; These are PbFree Devices

Use the download button to access the MC74HC4094ADR2G schematic symbol, PCB footprint, and 3D model.

Low Crosstalk Between Switches; Fast Switching and Propagation Speeds; Chip Complexity: HC4051A - 184 FETs or 46 Equivalent Gates HC4052A - 168 FETs or 42 Equivalent Gates HC4053A - 156 FETs or 39 Equivalent Gates; Analog Power Supply Range (VCC - VEE ) = 2.0 to 12.0 V; In Compliance With the Requirements of JEDEC Standard No. 7A; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Diode Protection on All Inputs/Outputs; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; L

Low Crosstalk Between Switches; Fast Switching and Propagation Speeds; Chip Complexity: HC4051A - 184 FETs or 46 Equivalent Gates HC4052A - 168 FETs or 42 Equivalent Gates HC4053A - 156 FETs or 39 Equivalent Gates; Analog Power Supply Range (VCC - VEE ) = 2.0 to 12.0 V; In Compliance With the Requirements of JEDEC Standard No. 7A; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Diode Protection on All Inputs/Outputs; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; L

Use the download button to access the MC74HC4053ADTG schematic symbol, PCB footprint, and 3D model.

Chip Complexity: 398 FETs or 99.5 Equivalent Gates; Output Drive Capability: 10 LSTTL Loads; In Compliance With JEDEC Standard No. 7A Requirements; Low Input Current: 1 uA; Outputs Directly Interface to CMOS, NMOS, and TTL; Operating Voltage Range: 2 to 6 V; High Noise Immunity Characteristic of CMOS Devices; Pb-Free Packages are Available*

Low Crosstalk Between Switches; Fast Switching and Propagation Speeds; Chip Complexity: HC4051A - 184 FETs or 46 Equivalent Gates HC4052A - 168 FETs or 42 Equivalent Gates HC4053A - 156 FETs or 39 Equivalent Gates; Analog Power Supply Range (VCC - VEE ) = 2.0 to 12.0 V; In Compliance With the Requirements of JEDEC Standard No. 7A; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Diode Protection on All Inputs/Outputs; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; L

Output Drive Capability: 10 LSTTL Loads; High Noise Immunity Characteristic of CMOS Devices; Chip Complexity: 236 FETs or 59 Equivalent Gates; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Operating Voltage Range: 2 to 6 V; Low Input Current: 1 mA; Outputs Directly Interface to CMOS, NMOS, and TTL; Pb-Free Packages are Available

MC74HC4052ADTG ON Semiconductor, Multiplexer/Demultiplexer Single 8:1, 2 → 12 V, 2 → 6 V, 16-Pin TSSOP

Diode Protection on All Inputs/Outputs; Chip Complexity: 44 FETs or 11 Equivalent Gates; High ON/OFF Output Voltage Ratio; Fast Switching and Propagation Speeds; Low Crosstalk Between Switches; Analog Input Voltage Range (VCC - GND) = 2.0 to 12.0 Volts; Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066; Low Noise; Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 12.0 Volts; Pb-Free Packages are Available*

Low Crosstalk Between Switches; Fast Switching and Propagation Speeds; Chip Complexity: HC4051A - 184 FETs or 46 Equivalent Gates HC4052A - 168 FETs or 42 Equivalent Gates HC4053A - 156 FETs or 39 Equivalent Gates; Analog Power Supply Range (VCC - VEE ) = 2.0 to 12.0 V; In Compliance With the Requirements of JEDEC Standard No. 7A; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Diode Protection on All Inputs/Outputs; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; L

Outputs Directly Interface to CMOS, NMOS and TTL; Low Input Current: 1mA; High Noise Immunity Characteristic of CMOS Devices; Chip Complexity: 48 FETs or 12 Equivalent Gates; Output Drive Capability: 10 LSTTL Loads; In Compliance With the JEDEC Standard No. 7A Requirements; Operating Voltage Range: 2 to 6V; Pb-Free Packages are Available

In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Outputs Directly Interface to CMOS, NMOS and TTL; Chip Complexity: 264 FETs or 66 Equivalent Gates; High Noise Immunity Characteristic of CMOS Devices; Output Drive Capability: 10 LSTTL Loads; Operating Voltage Range: 2.0 to 6.0 V; Low Input Current: 1.0 mA; Pb-Free Packages are Available*

Output Drive Capability: 10 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS, and TTL; Operating Voltage Range: 2 to 6 V; Low Input Current: 1 A; High Noise Immunity Characteristic of CMOS Devices; These are PbFree Devices

Output Drive Capability: 15 LSTTL Loads; Operating Voltage Range: 2 to 6 V; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1 mA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 136 FETs or 34 Equivalent Gates; Pb-Free Packages are Available*

Output Drive Capability: 15 LSTTL Loads; Operating Voltage Range: 2 to 6 V; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1 mA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 136 FETs or 34 Equivalent Gates; Pb-Free Packages are Available*

Output Drive Capability: 15 LSTTL Loads; Operating Voltage Range: 2 to 6 V; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1 mA; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 136 FETs or 34 Equivalent Gates; Pb-Free Packages are Available*

TSOP-5

SOP-16

High Noise Immunity; High Speed: tPD = 7ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1mA (Max) at TA = 25°C; Balanced Propagation Delays (tpLH = tpHL); Symmetrical Output Impedance (IOH = IOL = 2mA); Chip Complexity: FET = 101

High Noise Immunity; High Speed: tPD = 7ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1mA (Max) at TA = 25°C; Balanced Propagation Delays (tpLH = tpHL); Symmetrical Output Impedance (IOH = IOL = 2mA); Chip Complexity: FET = 101

High Noise Immunity; Low Power Dissipation: ICC = 1mA (Max) at TA = 25°C; Symmetrical Output Impedance (IOH = IOL = 2mA); High Speed: tPD = 7ns (Typ) at VCC = 5V; Balanced Propagation Delays (tpLH = tpHL); Chip Complexity: FET = 44; Equivalent Gate = 11; Pb-Free Packages are Available; Designed for 2.0 V to 6.0 V Vcc Operation Wide Operating Vcc Range

Output Drive Capability: 10 LSTTL Loads; Operating Voltage Range: 2 to 6V; Outputs Directly Interface to CMOS, NMOS and TTL; Low Input Current: 1mA; In Compliance With the JEDEC Standard No. 7A Requirements; Chip Complexity: 60 FETs or 15 Equivalent Gates; High Noise Immunity Characteristic of CMOS Devices; Pb-Free Packages are Available