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Low Input Current: 1.0 mA; Operating Voltage Range: 4.5 to 5.5 V; Output Drive Capability: 10 LSTTL Loads; Chip Complexity: 136 FETs or 34 Equivalent Gates; Outputs Directly Interface to CMOS, NMOS, and TTL; TTL NMOS Compatible Input Levels; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Pb-Free Packages are Available

Output Drive Capability: 10 LSTTL Loads; Low Input Current: 1mA; Outputs Directly Interface to CMOS, NMOS and TTL; Chip Complexity: 48 FETs or 12 Equivalent Gates; In Compliance With the JEDEC Standard No. 7A Requirements; Operating Voltage Range: 4.5 to 5.5V; TTL/NMOS-Compatible Input Levels; Pb-Free Packages are Available

Low Input Current: 1 mA; Operating Voltage Range: 2 to 6 V; High Noise Immunity Characteristic of CMOS Devices; Chip Complexity: 526 FETs or 131.5 Equivalent Gates; Output Drive Capability: 15 LSTTL Loads; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Outputs Directly Interface to CMOS, NMOS, and TTL; Pb-Free Packages are Available

Outputs Directly Interface to CMOS, NMOS and TTL; Output Drive Capability: 15 LSTTL Loads; High Noise Immunity Characteristic of CMOS Devices; Low Input Current: 1mA; In Compliance With the JEDEC Standard No. 7A Requirements; Chip Complexity: 124 FETs or 31 Equivalent Gates; Operating Voltage Range: 2 to 6V; Pb-Free Packages are Available*

ON Semiconductor MC74HC4052ADWG, Multiplexer/Demultiplexer Single 8:1, 2 → 12 V, 2 → 6 V, 16-Pin SOIC

Symmetrical Output Impedance (IOH = IOL = 2mA); Balanced Propagation Delays (tpLH = tpHL); Low Power Dissipation: ICC = 1mA (Max) at TA = 25°C; High Speed: tPD = 7ns (Typ) at VCC = 5V; High Noise Immunity; Chip Complexity: FET = 105; Equivalent Gate = 26

High Speed: tPD = 7ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1mA (Max) at TA = 25°C; High Noise Immunity; Balanced Propagation Delays (tpLH = tpHL); Symmetrical Output Impedance (IOH = IOL = 2mA); Chip Complexity: FET = 105; Equivalent Gate = 26

High Noise Immunity; Balanced Propagation Delays (tpLH = tpHL); Low Power Dissipation: ICC = 1mA (Max) at TA = 25°C; Symmetrical Output Impedance (IOH = IOL = 2mA); High Speed: tPD = 7ns (Typ) at VCC = 5V; Chip Complexity: FETs = <100

Chip Complexity 166 FETs or 41.5 Equivalent Gates; Output Drive Capability: 10 LSTTL Loads; High Noise Immunity Characteristic of CMOS Devices; Outputs Directly Interface to CMOS, NMOS, and TTL; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Low Input Current: 1 mA; Operating Voltage Range: 2 to 6 V; Pb-Free Packages are Available*

In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1 mA; Chip Complexity: 286 FETs or 71.5 Equivalent Gates; Operating Voltage Range: 2 to 6 V; High Noise Immunity Characteristic of CMOS Devices; Output Drive Capability: 10 LSTTL Loads; Pb-Free Packages are Available*

Outputs Directly Interface to CMOS, NMOS, and TTL; Output Drive Capability: 10 LSTTL Loads; Chip Complexity: 244 FETs or 61 Equivalent Gates; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; High Noise Immunity Characteristic of CMOS Devices; Low Input Current: 1 mA; Operating Voltage Range: 2 to 6 V; Pb-Free Packages are Available

Chip Complexity: 82 FETs or 20.5 Equivalent Gates; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Low Input Current: 1.0 mA; Operating Voltage Range: 2.0 to 6.0 V; High Noise Immunity Characteristic of CMOS Devices; Outputs Directly Interface to CMOS, NMOS, and TTL; Output Drive Capability: 10 LSTTL Loads; Pb-Free Packages are Available*

Low Input Current: 1.0 mA; Chip Complexity: 100 FETs or 25 Equivalent Gates; Operating Voltage Range: 2.0 to 6.0 V; Outputs Directly Interface to CMOS, NMOS and TTL; Output Drive Capability: 10 LSTTL Loads; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Pb-Free Packages are Available*

PDIP-8

SOIC-8 Narrow Body-8

Precision 2% Reference; Standby Mode Reduces Power Supply Current to 36 µA; Provides 5.05 V Output without External Resistor Divider; Internal Thermal Shutdown; Cycle-by-Cycle Current Limiting; Economical 5-Lead TO-220 Package with Two Optional Leadforms; Undervoltage Lockout with Hysteresis; 0% to 95% Output Duty Cycle; Operation from 7.5 V to 40 V; Fixed Frequency Oscillator (72 kHz) with On-Chip Timing; Output Switch Current in Excess of 5.0 A; Moisture Sensitivity Level (MSL) Equals 1; Also Available in

High Slew Rate: 13 V/µs; Large Output Voltage Swing: -14.7 V to +14 V (with +/-15 V Supplies); Excellent Gain Margin: 12 dB; Wide Bandwidth: 4.5 MHz; Fast Settling Time: 1.1 µs to 0.1%; Low Input Offset Voltage: 3.0 mV Maximum (A Suffix); Output Short Circuit Protection; Large Capacitance Drive Capability: 0 pF to 10,000 pF; Low Total Harmonic Distortion: 0.02%; Excellent Phase Margin: 60° Wide Input Common Mode Voltage Range: Includes Ground (VEE); Wide Single Supply Operation: 3.0 V to 44 V

High Slew Rate: 13 V/µs; Large Output Voltage Swing: -14.7 V to +14 V (with +/-15 V Supplies); Excellent Gain Margin: 12 dB; Wide Bandwidth: 4.5 MHz; Fast Settling Time: 1.1 µs to 0.1%; Low Input Offset Voltage: 3.0 mV Maximum (A Suffix); Output Short Circuit Protection; Large Capacitance Drive Capability: 0 pF to 10,000 pF; Low Total Harmonic Distortion: 0.02%; Excellent Phase Margin: 60° Wide Input Common Mode Voltage Range: Includes Ground (VEE); Wide Single Supply Operation: 3.0 V to 44 V

High Slew Rate: 13 V/µs; Large Output Voltage Swing: -14.7 V to +14 V (with +/-15 V Supplies); Excellent Gain Margin: 12 dB; Wide Bandwidth: 4.5 MHz; Fast Settling Time: 1.1 µs to 0.1%; Low Input Offset Voltage: 3.0 mV Maximum (A Suffix); Output Short Circuit Protection; Large Capacitance Drive Capability: 0 pF to 10,000 pF; Low Total Harmonic Distortion: 0.02%; Excellent Phase Margin: 60° Wide Input Common Mode Voltage Range: Includes Ground (VEE); Wide Single Supply Operation: 3.0 V to 44 V

SOIC-14