VCC6-QCD-25M0000000 Microchip Crystal or Oscillator (Other) In Stock
VCC6-QCD-25M0000000 is a 25 MHz LVPECL standard clock oscillator from Microchip operating on 3.3 V supply with ±50 ppm frequency stability and complementary differential outputs. It features an enable/disable function and fast 0.6 ns maximum fall time in a compact LDFN-6 surface-mount package rated –40°C to +85°C. Available worldwide with RoHS e4 lead-free compliance.
- Manufacturer
- Microchip
- Package
- Other
- Pin Count
- 6
- Lifecycle
- OBSOLETE
- Datasheet
- VCC6-QCD-25M0000000 Datasheet PDF
- Category
- Crystal or Oscillator
- Price
- From $11.7600(MOQ 100)
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 25 MHz LVPECL differential complementary outputs with 0.6 ns maximum fall time, enabling low-jitter clock distribution in high-speed serial and networking circuits on a 3.3 V supply
- Enable/disable control pin allows power-gating of the oscillator output for reduced system power consumption or clock multiplexing without additional logic gates
- ±50 ppm frequency stability over –40°C to +85°C in a compact LDFN-6 surface-mount package simplifies industrial and networking equipment clock tree design
Applications
VCC6-QCD-25M0000000 provides the 25 MHz reference clock required by Gigabit Ethernet PHY and SGMII link interfaces, where LVPECL outputs minimise signal integrity degradation across differential PCB traces. Its enable/disable pin supports clock-gating strategies in energy-efficient network switches and industrial Ethernet modules, reducing idle-mode power. The –40°C to +85°C industrial temperature range and 50 ppm stability also suit optical transceiver timing references and PCIe endpoint clock sources.
Specifications
| Manufacturer Package Code | LDFN-6 |
| Factory Lead Time | 9Weeks |
| YTEOL | 0 |
| Additional Feature | ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT |
| Fall Time-Max | 0.6ns |
| Frequency Adjustment-Mechanical | NO |
| Frequency Stability | 50% |
| JESD-609 Code | e4 |
| Mounting Feature | SURFACE MOUNT |
| Operating Frequency-Nom | 25MHz |
| Oscillator Type | LVPECL |
| Output Load | 50OHM |
| Package Body Material | CERAMIC |
| Package Equivalence Code | DILCC6,.2 |
| Physical Dimension | 7.0mm x 5.0mm x 1.6mm |
| Qualification Status | Not Qualified |
| Rise Time-Max | 0.6ns |
| Supply Current-Max | 98mA |
| Supply Voltage-Max | 3.465V |
| Supply Voltage-Min | 3.135V |
| Supply Voltage-Nom | 3.3V |
| Surface Mount | YES |
| Symmetry-Max | 55/45 % |
| Terminal Finish | Gold (Au) - with Nickel (Ni) barrier |
| Package | Other |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| ECCN | EAR99 |
| HTS Code | 8542.31.00.01 |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
Why choose LVPECL output from VCC6-QCD-25M0000000 over LVCMOS for a Gigabit Ethernet PHY reference clock?
LVPECL differential output reduces susceptibility to common-mode noise and power-supply-induced jitter by 10 dB to 15 dB compared to single-ended LVCMOS, critical for Gigabit Ethernet PHY clock inputs that specify less than 50 ps RMS phase jitter. The complementary output pair also doubles noise immunity margin on a 100 Ω differential trace. At 25 MHz with a 0.6 ns maximum fall time, VCC6-QCD-25M0000000 meets the Gigabit Ethernet reference clock slew rate requirement without external termination networks.
How does the enable/disable function of VCC6-QCD-25M0000000 support power management in a multi-port network switch?
The enable/disable control pin on VCC6-QCD-25M0000000 allows the system MCU or FPGA to gate the 25 MHz clock output when downstream PHY ports are in link-down or low-power state. Disabling the oscillator output reduces dynamic current by typically 5 mA to 10 mA at 3.3 V per disabled oscillator, contributing to IEEE 802.3az Energy-Efficient Ethernet power savings in a 24-port switch with multiple 25 MHz references. Re-enabling the oscillator restores the clock within the oscillator's specified start-up time, typically under 10 ms.
What board layout considerations apply to the LDFN-6 package of VCC6-QCD-25M0000000 for minimising phase noise?
The LDFN-6 (leadless DFN) package exposes a thermal pad on the underside for soldering, providing low-inductance ground connection that reduces package-to-board resonance compared to leaded packages. For LVPECL outputs, a 100 Ω differential termination resistor placed within 10 mm of the output pins minimises reflections on traces longer than 20 mm at 25 MHz. A 100 nF bypass capacitor on the 3.3 V supply pin placed within 2 mm of the package suppresses supply noise coupling into the oscillator, keeping phase noise below –130 dBc/Hz at 1 kHz offset.
For a PCIe Gen 1 application, does the ±50 ppm stability of VCC6-QCD-25M0000000 meet the reference clock specification?
PCIe Gen 1 specifies a 100 MHz reference clock (or 25 MHz with PLL multiplication), with a frequency accuracy of ±300 ppm and phase jitter of under 1 ps RMS (12 kHz to 20 MHz). VCC6-QCD-25M0000000's ±50 ppm stability is well within the frequency accuracy budget. However, after PLL multiplication to 100 MHz, the phase jitter contribution of the 25 MHz source must be verified against the PCIe CEM specification—the 0.6 ns maximum fall time and LVPECL logic family typically satisfy PCIe Gen 1 jitter requirements when an appropriate PLL filter bandwidth of 1 MHz to 5 MHz is selected.
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| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 100+ | $12.3200 | $1232.00 |
| 1000+ | $11.8900 | $11890.00 |
| 5000+ | $11.7600 | $58800.00 |
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