TPD1E0B04DPLR Texas Instruments Inductor (Other) In Stock
The TPD1E0B04DPLR is a single-channel silicon transient voltage suppressor diode with a 6.7 V breakdown voltage and a maximum clamping voltage of 7.2 V in a 2-pin SOD-882 package. It protects a single I/O line from ESD events and voltage transients with a sub-picosecond response time. Available from stock with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Other
- Pin Count
- 2
- Lifecycle
- ACTIVE
- Datasheet
- TPD1E0B04DPLR Datasheet PDF
- Category
- Inductor
- Temp Range
- -40.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 6.7 V breakdown and 7.2 V clamping voltage provides tight overvoltage protection for 5 V and 3.3 V logic I/O lines in compact designs
- Single-channel TVS in ultra-compact 2-pin SOD-882 package occupies under 0.3 mm2 of PCB area for space-constrained portable designs
- Silicon TVS technology delivers sub-nanosecond clamping response to IEC 61000-4-2 ESD events up to 8 kV contact discharge
- Single 1-channel configuration allows precise per-pin ESD protection placement adjacent to connector or port I/O on high-density PCBs
Applications
The TPD1E0B04DPLR is designed to protect single I/O lines on smartphones, tablets, and wearable devices against ESD strikes at USB, headset, and button interfaces where board space allows only a 0.3 mm x 0.45 mm SOD-882 footprint. It is also used on HDMI, MIPI, and GPIO pins of FPGA evaluation boards and industrial IoT sensor nodes where individual signal lines require low-capacitance transient clamping without degrading signal integrity. The tight 7.2 V clamp voltage makes it suitable for protecting 5 V-tolerant input pins directly without risk of forward-biasing the downstream logic input protection diodes.
Specifications
| Pbfree Code | Yes |
| Date Of Intro | 2016-04-02 |
| YTEOL | 15 |
| Breakdown Voltage-Min | 6.7V |
| Breakdown Voltage-Nom | 6.7V |
| Clamping Voltage-Max | 7.2V |
| Configuration | SINGLE, 1 CHANNEL |
| Diode Element Material | SILICON |
| Diode Type | TRANS VOLTAGE SUPPRESSOR DIODE |
| JESD-30 Code | R-PBCC-N2 |
| JESD-609 Code | e4 |
| Non-rep Peak Rev Power Dis-Max | 15W |
| Number of Elements | 1 |
| Package Body Material | PLASTIC/EPOXY |
| Package Shape | RECTANGULAR |
| Package Style | CHIP CARRIER |
| Peak Reflow Temperature (Cel) | 260 |
| Polarity | BIDIRECTIONAL |
| Reference Standard | IEC-61000-4-2, 4-4, 4-5 |
| Rep Pk Reverse Voltage-Max | 3.6V |
| Reverse Current-Max | 0.01 µA |
| Reverse Test Voltage | 2.5V |
| Surface Mount | YES |
| Technology | AVALANCHE |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | NO LEAD |
| Terminal Position | BOTTOM |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Other |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8541.10.00.80 |
Alternate & Equivalent Parts
Compatible alternatives and drop-in replacements for TPD1E0B04DPLR:
suggested
Frequently Asked Questions
What clamping voltage does the TPD1E0B04DPLR hold during an ESD event, and why does this protect 5 V logic?
The TPD1E0B04DPLR clamps to a maximum of 7.2 V during a transient event, which is safely below the 8 V absolute maximum input voltage of most 5 V CMOS logic ICs. This 7.2 V clamp absorbs the energy of an ESD pulse up to 8 kV (IEC 61000-4-2 contact discharge) and limits the voltage seen by the downstream component to a non-destructive level within nanoseconds of the event onset.
How small is the TPD1E0B04DPLR package, and how does it fit on a smartphone PCB?
The device is housed in a 2-pin SOD-882 package measuring 0.30 mm x 0.45 mm, which is one of the smallest commercially available TVS packages. This footprint is small enough to place directly at a USB Type-C connector pin or headset jack pin on a smartphone main PCB without impacting the board routing channel, even in designs with a 0.1 mm clearance rule between components.
What is the breakdown voltage of the TPD1E0B04DPLR, and how does it affect its use on a 3.3 V logic rail?
The breakdown voltage is 6.7 V minimum, which provides more than 3 V of headroom above the 3.3 V signal peak before the TVS begins conducting. This margin ensures the device remains in its non-conducting state during normal 3.3 V signal swings, introducing no current leakage or capacitive loading beyond the device's inherent junction capacitance of typically under 0.5 pF, which preserves high-frequency signal integrity up to several GHz.
When is the TPD1E0B04DPLR preferred over a multi-channel TVS array for a USB or HDMI interface?
A single-channel TPD1E0B04DPLR is preferred when only 1 specific I/O line requires protection — for example, a GPIO button line or a VBUS sense pin — and placing a 4-channel or 8-channel array would waste 3 to 7 unused channels and add parasitic capacitance of 0.3 to 0.5 pF per unused diode to adjacent signal traces. For full USB 3.0 or HDMI 2.0 port protection with 5 to 8 differential pairs, a multi-channel array is more area efficient.
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