SN74LVTH373PWG4 Texas Instruments Integrated Circuit (Small Outline Packages) In Stock
The SN74LVTH373PWG4 is an octal transparent D-type latch from Texas Instruments in the 3.3V LVT logic family, housed in a 20-pin TSSOP package. It features active-low output enable control and drives 8 data lines at up to 64mA sink current with 50pF load capacity. Available from stock worldwide for bus interface and memory address latch designs.
- Manufacturer
- Texas Instruments
- Package
- Small Outline Packages
- Pin Count
- 20
- Lifecycle
- OBSOLETE
- Datasheet
- SN74LVTH373PWG4 Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of SN74LVTH373PWG4?
- 8-bit transparent D-type latch with active-low output enable for address and data bus hold applications
- 3.3V LVT family accepts 5V-tolerant inputs enabling direct interfacing between 3.3V and 5V logic buses
- 20-pin TSSOP package with 64mA output sink current drives high-capacitance backplane and memory bus loads
What is SN74LVTH373PWG4 used for?
The SN74LVTH373PWG4 is widely used as an address latch in microcontroller and DSP memory bus systems where 8 address bits must be held stable during a multiplexed bus cycle. Its transparent latch mode allows real-time data flow when the enable is asserted, then latches the state when deasserted, making it ideal for demultiplexing address-data buses. The 3.3V LVT family with 5V-tolerant inputs also enables direct bridging between legacy 5V peripherals and modern 3.3V processor buses.
What are the specifications of SN74LVTH373PWG4?
| YTEOL | 0 |
| Control Type | ENABLE LOW |
| Count Direction | UNIDIRECTIONAL |
| Family | LVT |
| JESD-30 Code | R-PDSO-G20 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | BUS DRIVER |
| Max I(ol) | 0.064A |
| Number of Bits | 8 |
| Number of Functions | 1 |
| Number of Ports | 2 |
| Output Characteristics | 3-STATE |
| Output Polarity | TRUE |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | TSSOP20,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| Packing Method | TUBE |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 5mA |
| Prop. Delay@Nom-Sup | 3.9ns |
| Propagation Delay (tpd) | 4.9ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Supply Voltage-Nom (Vsup) | 3.3V |
| Surface Mount | YES |
| Technology | BICMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.65mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Trigger Type | HIGH LEVEL |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| HTS Code | 8542.39.00.60 |
Where can I find the SN74LVTH373PWG4 datasheet?
SN74LVTH373PWG4 Datasheet DownloadOfficial datasheet from Texas Instruments
What are equivalent replacements for SN74LVTH373PWG4?
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
What output drive current can the SN74LVTH373PWG4 sink, and what load capacitance is it rated for?
The SN74LVTH373PWG4 provides a maximum output sink current of 64mA and is characterized at a load capacitance of 50pF. This combination allows it to drive high-capacitance bus lines such as SRAM address lines or backplane traces without external buffers, reducing component count in embedded microprocessor memory interface designs operating from a 3.3V supply.
How does the transparent latch mode of the SN74LVTH373PWG4 work in a multiplexed address-data bus design?
In transparent mode, with the active-low output enable asserted, all 8 D inputs pass directly to the Q outputs. When the latch enable is deasserted, the last input state is captured and held regardless of subsequent input changes. This allows a microcontroller to assert ALE, briefly present the 8-bit address on the shared bus, then release the bus for data transfer while the latch holds the address stable for the memory device.
Can the SN74LVTH373PWG4 interface a 3.3V microcontroller to 5V legacy SRAM or peripheral chips?
Yes. The SN74LVTH373PWG4 belongs to the LVT (Low Voltage Technology) family which operates from 3.3V VCC but accepts input voltages up to 5.5V, making it fully 5V-tolerant on its data inputs. This allows a 3.3V microcontroller or FPGA to drive the latch inputs directly while the 8 outputs drive a 5V SRAM or peripheral, simplifying mixed-voltage PCB designs without the need for separate level-translation ICs.
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About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
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