SN74LVT573PWR Texas Instruments Integrated Circuit (Small Outline Packages) In Stock
The SN74LVT573PWR is a 3.3V ABT octal transparent D-type latch with 3-state outputs from Texas Instruments, featuring bus hold inputs and compatibility with both 3.3V and 5V driver devices in a 20-pin TSSOP package. It provides active-low output enable and latch enable controls for flexible bus data storage applications. Available from stock with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Small Outline Packages
- Pin Count
- 20
- Lifecycle
- ACTIVE
- Datasheet
- SN74LVT573PWR Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 3.3V LVT family octal transparent D-type latch fully compatible with inputs driven by 3.3V or 5V logic, enabling seamless mixed-voltage bus interfacing
- Bus hold inputs maintain the last driven logic state when inputs are floating or tri-stated, eliminating external pull-up/pull-down resistors and reducing bus noise
- Active-low output enable (OE) and latch enable with 3-state outputs allow multiple SN74LVT573PWR devices to share a common bus without signal contention
- Compact 20-pin TSSOP package (JESD-30 R-PDSO-G20) with RoHS-compliant Pb-free construction and 50pF load capacitance support for modern PCB designs
Applications
The SN74LVT573PWR is widely used in microprocessor and microcontroller address and data bus systems for address latching, data buffering, and bus isolation in 3.3V and mixed 3.3V/5V embedded designs. It is also applied in memory interface circuits, FPGA peripheral logic, and PLD-based systems that require 8-bit transparent data latching with bus-hold capability to prevent floating inputs. Its 5V-input tolerance makes it an ideal interface bridge between legacy 5V peripherals and modern 3.3V processor buses.
Specifications
| Pbfree Code | Yes |
| Date Of Intro | 1992-03-01 |
| YTEOL | 15 |
| Additional Feature | BROADSIDE VERSION OF 373; INPUTS CAN BE DRIVEN BY 3.3/5V DEVICES; BUS HOLD INPUTS |
| Control Type | ENABLE LOW/HIGH |
| Count Direction | UNIDIRECTIONAL |
| Family | LVT |
| JESD-30 Code | R-PDSO-G20 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | BUS DRIVER |
| Max I(ol) | 0.016A |
| Number of Bits | 8 |
| Number of Functions | 8 |
| Number of Ports | 2 |
| Output Characteristics | 3-STATE |
| Output Polarity | TRUE |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | TSSOP20,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| Packing Method | TR |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 5mA |
| Prop. Delay@Nom-Sup | 4.3ns |
| Propagation Delay (tpd) | 7.2ns |
| Qualification Status | Not Qualified |
| Screening Level | MIL-STD-883 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Supply Voltage-Nom (Vsup) | 3.3V |
| Surface Mount | YES |
| Technology | BICMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.65mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.90 |
| Country of Origin | Malaysia |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
What does the bus hold feature do in the SN74LVT573PWR?
The bus hold feature maintains the last driven logic level (high or low) on each input when the driving source is removed or tri-stated. This prevents undefined or floating input states that can cause excessive current consumption or logic errors, eliminating the need for external pull-up or pull-down resistors on bus lines.
Is the SN74LVT573PWR compatible with 5V logic inputs despite being a 3.3V device?
Yes, the SN74LVT573PWR has input pins that can be driven directly by 3.3V or 5V logic devices. This mixed-voltage tolerance is a key feature of the LVT (Low Voltage Technology) family, making it an ideal interface component in systems that mix legacy 5V ICs with modern 3.3V processors and FPGAs.
How do the latch enable and output enable pins work on the SN74LVT573PWR?
The SN74LVT573PWR has an active-high latch enable (LE): when LE is high, outputs follow the D inputs (transparent mode); when LE goes low, inputs are captured and held. The active-low output enable (OE) controls the 3-state outputs: when OE is low, outputs drive the bus; when OE is high, all outputs go high-impedance to release the bus.
What is the difference between the SN74LVT573 and the SN74LVT373?
The SN74LVT573PWR is the broadside pinout version of the SN74LVT373, meaning the input (D) and output (Q) pins are arranged on opposite sides of the package. This layout simplifies PCB routing in bus applications by allowing input traces on one side and output traces on the other, reducing trace crossovers and board complexity.
What are typical applications for the SN74LVT573PWR?
Typical applications include address bus latching in microprocessor systems, data bus buffering and isolation, I/O port expansion, memory interface latching, and mixed 3.3V/5V bus bridging in embedded systems, industrial controllers, networking equipment, and computing boards requiring 8-bit transparent latching with tri-state output drive.
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About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
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