SN74LVC1G04DRYR Texas Instruments Integrated Circuit (Other) In Stock
The SN74LVC1G04DRYR is a single-gate CMOS inverter from the LVC logic family with 1.65V to 5.5V supply voltage range and 32mA output drive capability. It supports 50pF load capacitance in an ultra-compact 6-pin SOT-23 package. Available from stock with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Other
- Pin Count
- 6
- Lifecycle
- ACTIVE
- Datasheet
- SN74LVC1G04DRYR Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- -40.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- Single-gate LVC CMOS inverter enables minimal logic inversion without wasting multi-gate package resources
- 1.65V to 5.5V wide supply range allows mixed 1.8V, 3.3V, and 5V system interfacing
- 32mA output drive current supports direct driving of LEDs, capacitive lines, and bus signals
- Ultra-compact SOT-23 6-pin package ideal for space-critical logic glue in portable electronics
Applications
The SN74LVC1G04DRYR is widely used as a signal inverter and logic level buffer in digital systems requiring a single-gate solution without the overhead of larger logic packages. It is commonly deployed in microcontroller GPIO signal conditioning, clock inversion, and enable signal polarity conversion in IoT, mobile, and consumer electronics designs. The device is also used in industrial sensor interfaces and automotive electronics where reliable low-voltage logic operation across a wide supply range is required.
Specifications
| Pbfree Code | Yes |
| YTEOL | 15 |
| Family | LVC/LCX/Z |
| JESD-30 Code | R-PDSO-N6 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | INVERTER |
| Max I(ol) | 0.032A |
| Number of Functions | 1 |
| Number of Inputs | 1 |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | SOLCC6,.04,20 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, VERY THIN PROFILE |
| Packing Method | TR |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 0.01mA |
| Prop. Delay@Nom-Sup | 4.2ns |
| Propagation Delay (tpd) | 7.5ns |
| Qualification Status | Not Qualified |
| Schmitt Trigger | NO |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 1.65V |
| Supply Voltage-Nom (Vsup) | 3.3V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | AUTOMOTIVE |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | NO LEAD |
| Terminal Pitch | 0.5mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Other |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.90 |
Alternate & Equivalent Parts
Compatible alternatives and drop-in replacements for SN74LVC1G04DRYR:
Frequently Asked Questions
What supply voltage range does the SN74LVC1G04DRYR support?
The SN74LVC1G04DRYR operates from a supply voltage of 1.65V to 5.5V, making it compatible with 1.8V, 2.5V, 3.3V, and 5V logic systems. This wide operating range simplifies level shifting and interfacing across mixed-voltage digital designs.
What is the output drive current of the SN74LVC1G04DRYR?
The SN74LVC1G04DRYR provides a maximum low-level output current (IOL) of 32mA, which is sufficient for directly driving LEDs, capacitive bus lines up to 50pF, and other moderate-current logic loads without the need for a separate buffer stage.
What package does the SN74LVC1G04DRYR use?
The SN74LVC1G04DRYR is housed in a 6-pin SOT-23 package (JESD-30 code R-PDSO-N6), which is a miniature surface-mount plastic package suitable for high-density PCB assembly. It is lead-free (RoHS compliant) and compatible with standard reflow soldering processes.
How does the SN74LVC1G04DRYR differ from a standard 74HC04 hex inverter?
Unlike the 74HC04 which contains six inverter gates, the SN74LVC1G04DRYR contains a single gate in a tiny SOT-23 package. This allows designers to add exactly one inversion without wasting five unused gates, reducing board space, power consumption, and unused input management overhead in minimalist logic designs.
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