SN74LS375NE4 Texas Instruments Integrated Circuit (Dual-In-Line Packages) In Stock
The SN74LS375NE4 is a 4-channel transparent D-type latch in a 16-pin DIP package with 15 pF load capacitance and 8 mA low-level output current, providing reliable data latching for TTL logic systems. It is RoHS compliant and supports standard TTL voltage levels for interfacing data buses and register storage. Available from stock with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Dual-In-Line Packages
- Pin Count
- 16
- Lifecycle
- OBSOLETE
- Datasheet
- SN74LS375NE4 Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- ?°C to 70.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of SN74LS375NE4?
- 4-channel transparent D-type latch enables simultaneous storage of 4 data bits with a single enable signal
- 15 pF load capacitance supports driving standard TTL and LS logic inputs without additional buffering
- 16-pin DIP package with 8 mA output current suits through-hole prototyping and legacy digital designs
- RoHS compliant (e4 code) for use in environmentally regulated commercial and industrial end products
What is SN74LS375NE4 used for?
The SN74LS375NE4 is used in data bus interfacing, register file designs, and digital logic prototyping where 4-bit transparent latching is required with standard TTL voltage levels. Its 4-channel enable-controlled architecture allows nibble-wide data to be captured from a bus and held stable for downstream logic, making it suitable for address latches in legacy microprocessor bus designs, 4-bit output registers, and embedded control panel interfaces. The 16-pin DIP package supports both breadboard prototyping and through-hole PCB assembly for educational, industrial retrofit, and legacy system replacement applications.
What are the specifications of SN74LS375NE4?
| Pbfree Code | Yes |
| Reach Compliance Code | Compliant |
| YTEOL | 0 |
| Additional Feature | DUMMY VAL |
| Family | LS |
| JESD-30 Code | R-PDIP-T16 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 15pF |
| Logic IC Type | D LATCH |
| Max I(ol) | 0.008A |
| Number of Bits | 2 |
| Number of Functions | 2 |
| Output Polarity | COMPLEMENTARY |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | DIP16,.3 |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE |
| Packing Method | TUBE |
| Power Supply Current-Max (ICC) | 12mA |
| Prop. Delay@Nom-Sup | 27ns |
| Propagation Delay (tpd) | 30ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.25V |
| Supply Voltage-Min (Vsup) | 4.75V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | NO |
| Technology | TTL |
| Temperature Grade | COMMERCIAL |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| Trigger Type | POSITIVE EDGE |
| Package | Dual-In-Line Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| HTS Code | 8542.39.00.60 |
Where can I find the SN74LS375NE4 datasheet?
SN74LS375NE4 Datasheet DownloadOfficial datasheet from Texas Instruments
What are equivalent replacements for SN74LS375NE4?
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
How does the transparent latch function of the SN74LS375NE4 work in a data bus capture application?
In the SN74LS375NE4, when the enable input is high, the latch is transparent and the 4 Q outputs follow the 4 D inputs in real time; when enable goes low, the last state of each D input is latched and held on the Q outputs regardless of subsequent changes on D. This transparent-to-hold behavior lets a microprocessor assert a bus address for one clock phase and then latch it at 15 pF output load for downstream decoders during the next phase.
What is the output drive capability of the SN74LS375NE4, and how many standard LS loads can it drive?
The SN74LS375NE4 provides a maximum low-level output current of 8 mA and a rated load capacitance of 15 pF, which is sufficient to drive up to 10 standard LS TTL inputs in parallel without exceeding fanout limits. This drive capability supports typical bus expansion scenarios where the latch output feeds a data bus connected to memory decoders, I/O ports, or additional buffer stages in a 5 V TTL logic system.
For which prototyping scenarios is the SN74LS375NE4 in a 16-pin DIP package most practical compared to surface-mount alternatives?
The SN74LS375NE4 in the 16-pin DIP package is most practical for breadboard prototyping, repair of legacy industrial equipment, and educational lab exercises where through-hole components with 2.54 mm pin pitch can be inserted directly without soldering. It is also a common choice when replacing failed latches in older TTL-based systems still in service, as the 16-pin DIP footprint matches the original IC footprint in designs that predate surface-mount migration.
How does the SN74LS375NE4 compare to a D-type flip-flop for address bus latching in an 8-bit microprocessor system?
Unlike a D-type flip-flop that latches on a clock edge only, the SN74LS375NE4 transparent latch holds its outputs stable for as long as enable is low, making it better suited for address bus latching during long memory access cycles in 8-bit microprocessors such as Intel 8085 or Z80 where the ALE strobe is only 100 ns to 200 ns wide and the address must remain valid for several hundred nanoseconds afterward. The 4-channel width captures a full nibble per device, so two SN74LS375 latches can hold a complete 8-bit address.
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About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
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