SN74LS107ADG4 Texas Instruments Integrated Circuit (Small Outline Packages) In Stock
SN74LS107ADG4 is a dual negative-edge-triggered JK flip-flop IC in the LS TTL logic family, housed in a 14-pin SOIC package. Each element has independent J, K, clock, and active-low asynchronous clear inputs with complementary Q and Q-bar outputs. It supports a maximum toggle frequency of 30 MHz and is used in binary counters, shift registers, and digital state machines.
- Manufacturer
- Texas Instruments
- Package
- Small Outline Packages
- Pin Count
- 14
- Lifecycle
- OBSOLETE
- Datasheet
- SN74LS107ADG4 Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- ?°C to 70.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 2 independent negative-edge-triggered JK flip-flops with individual J, K, and clock inputs
- 30 MHz maximum toggle frequency in the LS (Low-power Schottky) logic family
- Asynchronous active-low direct clear for each flip-flop, independent of the clock
- Complementary Q and Q-bar outputs for toggle, divide-by-two, and feedback configurations
- 14-pin SOIC SMD package with 3.81 mm row spacing for compact PCB placement
- 8 mA sink current output compatible with LS and CMOS fanout requirements
Applications
SN74LS107ADG4 is used in digital frequency dividers, binary ripple counters, and synchronous state machines where negative-edge-triggered clocking and direct clear capability are required. It is a fundamental building block in educational electronics labs and legacy 5 V TTL circuit designs for clock division and sequence generation. Industrial programmable controllers and interface cards also use it as a simple 2-bit state element for handshake and ready/busy flag logic in bus arbitration circuits.
Specifications
| YTEOL | 0 |
| Family | LS |
| JESD-30 Code | R-PDSO-G14 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 15pF |
| Logic IC Type | J-K FLIP-FLOP |
| Max Frequency@Nom-Sup | 30000000Hz |
| Max I(ol) | 0.008A |
| Number of Bits | 2 |
| Number of Functions | 2 |
| Output Polarity | COMPLEMENTARY |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | SOP14,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE |
| Packing Method | TUBE |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 6mA |
| Prop. Delay@Nom-Sup | 20ns |
| Propagation Delay (tpd) | 20ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.25V |
| Supply Voltage-Min (Vsup) | 4.75V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | YES |
| Technology | TTL |
| Temperature Grade | COMMERCIAL |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Terminal Form | GULL WING |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Trigger Type | NEGATIVE EDGE |
| fmax-Min | 30MHz |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| HTS Code | 8542.39.00.60 |
Alternate & Equivalent Parts
Compatible alternatives and drop-in replacements for SN74LS107ADG4:
Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14
J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16
Frequently Asked Questions
How does the negative-edge triggering of SN74LS107ADG4 affect timing in a counter circuit?
SN74LS107ADG4 latches the J and K inputs and updates its outputs on the falling edge of the clock signal, meaning the flip-flop captures data during the high phase and transitions on the negative clock transition. In a ripple counter application, the Q-bar output of the first flip-flop drives the clock of the second, so each stage divides the frequency by 2. At 30 MHz maximum clock frequency, a 2-stage chain from SN74LS107ADG4 produces a divide-by-4 output at 7.5 MHz from a 30 MHz input clock.
Can the individual asynchronous clears on SN74LS107ADG4 be used to initialize a counter to a non-zero state?
The asynchronous direct clear on each flip-flop only forces the Q output to logic low, so it cannot directly preset a flip-flop to logic high. To initialize a counter to a non-zero state, the J and K inputs must be configured to load the desired bit value on the next clock edge while holding clear inactive. For example, setting J high and K low on a stage causes Q to go high on the next negative clock edge, achieving a programmed initial count without needing a separate preset pin.
What is the power supply voltage and current consumption for SN74LS107ADG4?
SN74LS107ADG4 operates from a 5 V supply with the LS-TTL input voltage thresholds of 0.8 V for logic low and 2.0 V for logic high. At 5 V, a typical LS-family dual flip-flop draws approximately 12 mA of quiescent supply current at maximum switching frequency. The 8 mA maximum output sink current per pin supports driving additional LS loads with a calculated fanout of up to 20 standard LS inputs without violating the I_OL specification.
Is SN74LS107ADG4 in a 14-pin SOIC pin-compatible with older 14-pin DIP versions of the 74107 device?
SN74LS107ADG4 is electrically and functionally pin-compatible with the 14-pin DIP 74LS107A, with the same pin numbering for J1, K1, CLK1, CLR1, Q1, Q1-bar, and their counterparts on the second flip-flop. The SOIC package has a smaller 3.81 mm row spacing and 1.27 mm pin pitch compared to the 7.62 mm row and 2.54 mm pitch of the DIP, so a PCB footprint change is required to migrate from through-hole to surface-mount but no firmware or logic changes are needed.
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About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
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