SN74HC05DBRE4 Texas Instruments Integrated Circuit (Small Outline Packages) In Stock

SN74HC05DBRE4 is a hex inverter IC with open-drain outputs in a 14-pin SOIC package from Texas Instruments HC logic family. It provides 6 independent single-input inverters rated at 50 pF load capacitance and 4 mA sink current. Lead-free and in stock worldwide.

OBSOLETEIntegrated CircuitVerified Jun 2026
Package / Visual Reference
SN74HC05DBRE4Small Outline Packages
Quick Facts
Manufacturer
Texas Instruments
Package
Small Outline Packages
Pin Count
14
Lifecycle
OBSOLETE
Category
Integrated Circuit
Temp Range
-40.0°C to 85.0°C
RoHS
Compliant
Lead Time
3–7 business days
Shipping
DHL Express · Worldwide

Key Features

  • 6 independent open-drain inverter channels in a single SOIC-14 package enable wired-AND bus configurations without external components
  • HC/UH family CMOS logic supports wide supply voltage operation with low quiescent current consumption
  • 4 mA open-drain output sink current allows direct interface with I2C pull-up lines and voltage level-shifting circuits
  • 50 pF rated load capacitance maintains signal integrity across moderately capacitive PCB trace loads

Applications

SN74HC05DBRE4 is used in digital interface circuits that require open-drain inversion, such as I2C bus buffering, wired-OR logic, and level-shifting between 3.3 V and 5 V systems. The open-drain outputs allow multiple devices to share a common pulled-up bus line, making this hex inverter a practical choice for inter-board communication and interrupt aggregation circuits. It also serves as a general-purpose logic inversion stage in microcontroller-based designs where individual signal polarities need to be reversed.

Specifications

Pbfree CodeYes
YTEOL0
FamilyHC/UH
JESD-30 CodeR-PDSO-G14
Load Capacitance (CL)50pF
Logic IC TypeINVERTER
Max I(ol)0.004A
Number of Functions6
Number of Inputs1
Output CharacteristicsOPEN-DRAIN
Package Body MaterialPLASTIC/EPOXY
Package Equivalence CodeSSOP14,.3
Package ShapeRECTANGULAR
Package StyleSMALL OUTLINE, SHRINK PITCH
Packing MethodTR
Peak Reflow Temperature (Cel)NOT SPECIFIED
Prop. Delay@Nom-Sup29ns
Propagation Delay (tpd)145ns
Qualification StatusNot Qualified
Schmitt TriggerNO
Supply Voltage-Max (Vsup)6V
Supply Voltage-Min (Vsup)2V
Supply Voltage-Nom (Vsup)4.5V
Surface MountYES
TechnologyCMOS
Temperature GradeINDUSTRIAL
Terminal FormGULL WING
Terminal Pitch0.65mm
Terminal PositionDUAL
Time@Peak Reflow Temperature-Max (s)NOT SPECIFIED
PackageSmall Outline Packages

Compliance & Regulatory

RoHS StatusCompliant
Lead-FreeYes (Pb-Free)
HTS Code8542.39.00.60

Datasheet

SN74HC05DBRE4 Datasheet Download

Official datasheet from Texas Instruments

Alternate & Equivalent Parts

No known alternates. Submit an RFQ and our team can suggest alternatives.

Frequently Asked Questions

What output configuration does SN74HC05DBRE4 use and how does that enable level-shifting between different logic voltages?

SN74HC05DBRE4 uses open-drain outputs, meaning each inverter output can only pull low—the high state is defined by an external pull-up resistor connected to any supply voltage the designer chooses. This allows a 3.3 V-logic input signal to be inverted and pulled up to a 5 V rail through an external resistor, achieving bidirectional voltage level-shifting without an external level-translator IC. Maximum sink current is 4 mA, which sets the minimum pull-up resistor value for a given supply voltage.

How many inverter channels does SN74HC05DBRE4 contain, and what is the rated load capacitance per channel?

SN74HC05DBRE4 provides 6 independent single-input inverter channels in its SOIC-14 package, each rated for a maximum load capacitance of 50 pF. The 6-channel count means a single device can invert an entire 6-bit bus or serve 6 separate signal lines simultaneously, reducing part count in multi-signal inversion designs compared to using individual inverter buffers.

For an I2C bus expander design, how does SN74HC05DBRE4 compare to a dedicated I2C buffer IC?

SN74HC05DBRE4 is a simpler and lower-cost option than a dedicated I2C buffer when the designer only needs passive open-drain inversion along the bus lines. Each channel sinks up to 4 mA, sufficient to pull down a standard I2C line with a 4.7 kΩ pull-up at 3.3 V or 5 V. However, a dedicated I2C buffer provides built-in capacitance isolation, automatic direction detection, and level translation in one device, making it better suited for long bus runs or mixed-voltage multi-master topologies.

Which SOIC package variant does SN74HC05DBRE4 use and what are the key PCB layout implications?

SN74HC05DBRE4 is housed in an SOIC-14 package (JEDEC MS-012) with a 1.27 mm lead pitch and a body width of 3.9 mm. This footprint is standard across HC logic families, so existing SOIC-14 pads designed for other hex logic ICs such as 74HC04 are pin-compatible with 74HC05 in most signal assignments. The narrow 3.9 mm body width allows dense placement alongside other SOIC logic in 0.1 inch-grid PCB designs.

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About Texas Instruments

Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.

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Lead Time3-7 business days
MOQFrom 1 piece
ShippingDHL / FedEx / UPS
OriginChina (Authorized)

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Their engineering team helped us find a pin-compatible alternative when our original MCU went EOL.

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CTO, AutoDrive Systems, Italy