SN74ACT7805-15DLR Texas Instruments Integrated Circuit (Small Outline Packages) In Stock

SN74ACT7805-15DLR is a synchronous 256 x 18-bit FIFO memory IC from Texas Instruments with 12 ns maximum access time and 67 MHz clock support, totaling 4608 bits of storage. It is housed in a 56-pin SOIC package optimized for high-speed data buffering designs. Available in reel format with worldwide shipping.

OBSOLETEIntegrated CircuitVerified Jun 2026
Package / Visual Reference
SN74ACT7805-15DLRSmall Outline Packages
Quick Facts
Manufacturer
Texas Instruments
Package
Small Outline Packages
Pin Count
56
Lifecycle
OBSOLETE
Category
Integrated Circuit
Temp Range
?°C to 70.0°C
RoHS
Compliant
Lead Time
3–7 business days
Shipping
DHL Express · Worldwide

Key Features

  • 256 x 18-bit synchronous FIFO with 4608-bit total capacity for buffering 18-bit wide data words in high-speed pipelines
  • 12 ns maximum access time and 67 MHz clock frequency supporting fast read/write cycles with 14.92 ns cycle time
  • 18-bit wide data path enabling byte-plus-parity or two-nibble data structures in a single device
  • 56-pin SOIC (R-PDSO-G56) package with SMT compatibility for compact high-speed board designs
  • Synchronous operation with clock-controlled read and write for predictable timing in clocked digital systems

Applications

The SN74ACT7805-15DLR is used in high-speed data flow control applications such as line-rate packet buffering between processors and network interfaces, where 18-bit wide data buses need FIFO decoupling to tolerate burst traffic without data loss. DSP systems that stream 18-bit audio samples between filter stages and DMA engines use it to absorb timing skew between source and sink clock domains. Legacy networking and telecom ASICs from the late 1990s and early 2000s often incorporated this FIFO for flow control between parallel bus interfaces operating at up to 67 MHz.

Specifications

Pbfree CodeNo
YTEOL0
Access Time-Max12ns
Clock Frequency-Max (fCLK)67MHz
Cycle Time14.92ns
JESD-30 CodeR-PDSO-G56
JESD-609 Codee4
Memory Density4608bit
Memory IC TypeOTHER FIFO
Memory Width18
Number of Functions1
Number of Words256words
Number of Words Code256
Operating ModeSYNCHRONOUS
Organization256X18
Output Characteristics3-STATE
Output EnableYES
Package Body MaterialPLASTIC/EPOXY
Package Equivalence CodeSSOP56,.4
Package ShapeRECTANGULAR
Package StyleSMALL OUTLINE, SHRINK PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Cel)260
Qualification StatusNot Qualified
Standby Current-Max0.0004A
Supply Voltage-Max (Vsup)5.5V
Supply Voltage-Min (Vsup)4.5V
Supply Voltage-Nom (Vsup)5V
Surface MountYES
TechnologyCMOS
Temperature GradeCOMMERCIAL
Terminal FinishNICKEL PALLADIUM GOLD
Terminal FormGULL WING
Terminal Pitch0.635mm
Terminal PositionDUAL
Time@Peak Reflow Temperature-Max (s)30
PackageSmall Outline Packages

Compliance & Regulatory

RoHS StatusCompliant
Lead-FreeYes (Pb-Free)
Moisture Sensitivity LevelMSL 1
ECCNEAR99
HTS Code8542.32.00.71

Datasheet

SN74ACT7805-15DLR Datasheet Download

Official datasheet from Texas Instruments

Alternate & Equivalent Parts

Compatible alternatives and drop-in replacements for SN74ACT7805-15DLR:

SN74ACT7805-15DLTexas Instruments

FIFO, 256X18, 12ns, Synchronous, CMOS, PDSO56

View Part →

Frequently Asked Questions

What is the data width and depth of the SN74ACT7805-15DLR FIFO, and how much total storage does it provide?

The SN74ACT7805-15DLR is a 256-word deep by 18-bit wide synchronous FIFO, providing 4608 bits (576 bytes) of total storage. The 18-bit width accommodates byte-plus-parity data structures common in error-checked bus interfaces and DSP pipelines, while the 256-word depth absorbs bursts of up to 256 data words before flagging a full condition to the write controller.

What maximum clock frequency and access time does SN74ACT7805-15DLR support for high-speed designs?

The SN74ACT7805-15DLR supports a maximum clock frequency of 67 MHz with a 14.92 ns cycle time and a maximum access time of 12 ns. These parameters allow it to sustain full-speed 18-bit data transfers in synchronous systems clocked at or below 67 MHz, making it compatible with late-1990s and early-2000s parallel bus architectures and DSP front-ends operating in the 50 MHz to 67 MHz range.

Is the SN74ACT7805-15DLR still in production, and what replacement options exist?

The SN74ACT7805-15DLR has a YTEOL of 0, meaning it is at end-of-life and no longer in active production. Engineers maintaining legacy boards should check distributor stock and consider IDT72V255 or similar synchronous FIFOs with comparable 256 x 18-bit depth and 12 ns access time. For new designs, modern FIFOs with deeper buffers, lower voltage, and LVTTL or LVCMOS interfaces offer significant improvements in power and density.

How does the 18-bit data width of SN74ACT7805-15DLR benefit parity-checked bus designs?

The 18-bit data width directly supports 16-bit data plus 2 parity bits, allowing the FIFO to store, propagate, and re-check parity through the buffer without stripping and re-generating parity outside the device. This is valuable in VMEbus, PCI, and custom parallel bus designs where end-to-end 16-bit parity coverage must be maintained across clock-domain crossings at bus speeds up to 67 MHz.

What package does the SN74ACT7805-15DLR use, and what PCB routing considerations apply?

The SN74ACT7805-15DLR is housed in a 56-pin SOIC (R-PDSO-G56) with 1.27 mm lead pitch. For 67 MHz operation, designers should keep data bus trace lengths under 5 cm and match clock-to-data skew within 1 ns, using 50-ohm controlled-impedance traces on a 4-layer stackup to minimize reflections and signal integrity degradation on the 18 output lines.

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About Texas Instruments

Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.

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Their engineering team helped us find a pin-compatible alternative when our original MCU went EOL.

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Marco Rossi
CTO, AutoDrive Systems, Italy