SN65LV1224ADBG4 Texas Instruments Integrated Circuit (Small Outline Packages) In Stock

Texas Instruments SN65LV1224ADBG4 is a 1:10 LVDS deserializer receiver supporting 100–660 Mbps serial data rates in a 28-pin SOIC package. Accepts differential LVDS input and recovers 10-bit parallel output data. Available in stock worldwide with competitive pricing.

OBSOLETEIntegrated CircuitVerified May 2026
Package / Visual Reference
SN65LV1224ADBG4Small Outline Packages
Quick Facts
Manufacturer
Texas Instruments
Package
Small Outline Packages
Pin Count
28
Lifecycle
OBSOLETE
Category
Integrated Circuit
Temp Range
-40.0°C to 85.0°C
RoHS
Compliant
Lead Time
3–7 business days
Shipping
DHL Express · Worldwide

What are the key features of SN65LV1224ADBG4?

  • 1:10 LVDS deserialization with 100–660 Mbps serial data rate range for high-speed data links
  • Differential LVDS input interface with robust noise immunity for long-distance signal transmission
  • 28-pin SOIC (R-PDSO-G28) package enabling compact PCB integration in space-constrained designs

What is SN65LV1224ADBG4 used for?

The SN65LV1224ADBG4 is well-suited for high-speed backplane and point-to-point serial link applications where parallel data must be reconstructed from a 660 Mbps differential stream. It is used in display interfaces, industrial communication buses, and test equipment requiring reliable LVDS deserialization at 100–660 Mbps. The device also fits video and imaging systems that need compact, low-power serial-to-parallel conversion in a 28-pin SOIC footprint.

What are the specifications of SN65LV1224ADBG4?

Pbfree CodeNo
YTEOL0
Driver Number of Bits1
High Level Input Current-Max0.0002A
Input CharacteristicsDIFFERENTIAL
Interface IC TypeLINE RECEIVER
Interface StandardGENERAL PURPOSE
JESD-30 CodeR-PDSO-G28
JESD-609 Codee4
Number of Functions1
Out Swing-Min0.35V
Output Low Current-Max0.005A
Output PolarityCOMPLEMENTARY
Package Body MaterialPLASTIC/EPOXY
Package Equivalence CodeSSOP28,.3
Package ShapeRECTANGULAR
Package StyleSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Cel)260
Qualification StatusNot Qualified
Receiver Number of Bits1
Supply Current-Max95mA
Supply Voltage-Max3.6V
Supply Voltage-Min3V
Supply Voltage-Nom3.3V
Supply Voltage1-Max3.6V
Supply Voltage1-Min3V
Supply Voltage1-Nom3.3V
Surface MountYES
TechnologyCMOS
Temperature GradeINDUSTRIAL
Terminal FinishNickel/Palladium/Gold (Ni/Pd/Au)
Terminal FormGULL WING
Terminal Pitch0.65mm
Terminal PositionDUAL
Time@Peak Reflow Temperature-Max (s)30
PackageSmall Outline Packages

Compliance & Regulatory

RoHS StatusCompliant
Lead-FreeYes (Pb-Free)
Moisture Sensitivity LevelMSL 1
ECCNEAR99
HTS Code8542.39.00.60

Where can I find the SN65LV1224ADBG4 datasheet?

SN65LV1224ADBG4 Datasheet Download

Official datasheet from Texas Instruments

What are equivalent replacements for SN65LV1224ADBG4?

Compatible alternatives and drop-in replacements for SN65LV1224ADBG4:

DS92LV1224TMSANational Semiconductor Corporation Line

Receiver, 1 Func, 1 Rcvr, CMOS, PDSO28

View Part →

Frequently Asked Questions

What is the maximum serial data rate supported by the SN65LV1224ADBG4?

The SN65LV1224ADBG4 supports serial data rates from 100 Mbps up to 660 Mbps, making it suitable for high-speed differential backplane links. This 1:10 deserialization ratio means the recovered parallel output runs at one-tenth the serial clock frequency, providing up to 66 MHz parallel output.

Which board-level interface standard does the SN65LV1224ADBG4 use for its input signal?

The device uses a differential LVDS (Low-Voltage Differential Signaling) input interface conforming to the general-purpose LVDS standard. LVDS inputs swing approximately 350 mV differentially around a 1.2 V common mode, giving excellent noise rejection over distances up to several meters at 660 Mbps.

How many output bits does the SN65LV1224ADBG4 recover from a single LVDS serial stream?

The SN65LV1224ADBG4 deserializes a single 1-bit LVDS serial input into a 10-bit parallel output word, with a 1:10 deserialization ratio. At the maximum 660 Mbps serial rate, this yields a 66 MHz parallel data bus with 10 bits per cycle, simplifying downstream FPGA or ASIC interface design.

What package does the SN65LV1224ADBG4 use and what are its pin count and lead-free status?

The SN65LV1224ADBG4 is housed in a 28-pin Small Outline IC (SOIC) package with a JESD-30 code of R-PDSO-G28. It is a non-lead-free variant (Pb-free Code: No). The 28-pin SOIC footprint is standard on most PCB design tools, easing board layout for high-speed serial receiver circuits.

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About Texas Instruments

Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.

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Lead Time3-7 business days
MOQFrom 1 piece
ShippingDHL / FedEx / UPS
OriginChina (Authorized)

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Their engineering team helped us find a pin-compatible alternative when our original MCU went EOL.

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Marco Rossi
CTO, AutoDrive Systems, Italy