LTC6994HS6-1#TRMPBF Analog Devices Integrated Circuit (SOT23 (6-Pin)) In Stock
Analog Devices LTC6994HS6-1#TRMPBF is a silicon programmable delay line with selectable rising or falling edge trigger in a 6-pin SOT-23 package. It provides a single-tap, resistor-configurable delay output for precise timing control. Compact and easy to configure for power sequencing and pulse delay applications.
- Manufacturer
- Analog Devices
- Package
- SOT23 (6-Pin)
- Pin Count
- 6
- Lifecycle
- ACTIVE
- Datasheet
- LTC6994HS6-1#TRMPBF Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $2.7500(MOQ 19)
- Temp Range
- -40.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of LTC6994HS6-1#TRMPBF?
- Silicon programmable delay line with rising or falling edge trigger selection
- Single-tap resistor-configurable delay for flexible timing without firmware
- Compact 6-pin SOT-23 package minimizing board footprint
- True output polarity with accurate delay range set by external resistor
What is LTC6994HS6-1#TRMPBF used for?
The LTC6994HS6-1#TRMPBF is used in power supply sequencing circuits where precise startup delays between rails must be enforced without a microcontroller. System designers use it to delay reset signals, watchdog timer triggers, or enable lines by a resistor-programmed interval ranging from microseconds to seconds, ensuring safe power-up ordering in multi-rail systems. Its small 6-pin SOT-23 footprint makes it easy to add delay functionality to space-constrained boards.
What are the specifications of LTC6994HS6-1#TRMPBF?
| Pbfree Code | No |
| Manufacturer Package Code | 05-08-1636 |
| YTEOL | 8.5 |
| Family | 6994 |
| JESD-30 Code | R-PDSO-G6 |
| JESD-609 Code | e3 |
| Logic IC Type | SILICON DELAY LINE |
| Number of Functions | 1 |
| Number of Taps/Steps | 1 |
| Output Polarity | TRUE |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | TSOP6,.11,37 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH |
| Packing Method | TR |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 0.2mA |
| Programmable Delay Line | YES |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2.25V |
| Supply Voltage-Nom (Vsup) | 3.3V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | AUTOMOTIVE |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.95mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | SOT23 (6-Pin) |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.01 |
| Country of Origin | Malaysia |
Where can I find the LTC6994HS6-1#TRMPBF datasheet?
LTC6994HS6-1#TRMPBF Datasheet DownloadOfficial datasheet from Analog Devices
What are equivalent replacements for LTC6994HS6-1#TRMPBF?
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
How is the delay time programmed in the LTC6994HS6-1#TRMPBF?
The delay time in the LTC6994HS6-1#TRMPBF is set by a single external resistor connected to the RSET pin. Varying the resistance changes the master oscillator frequency, which scales the delay duration across a wide range from approximately 1 µs to over 33 seconds, depending on the divider setting. No firmware or programming equipment is needed, making the configuration entirely hardware-defined and repeatable across production units.
Which power sequencing scenarios benefit from the LTC6994HS6-1#TRMPBF in a multi-rail system?
In systems with 3.3 V, 1.8 V, and 1.0 V rails that must power up in sequence, the LTC6994HS6-1#TRMPBF can delay the enable signal for each downstream rail by a resistor-set interval of tens of milliseconds after the upstream rail reaches regulation. This prevents inrush conflicts and protects ASICs or FPGAs that require their I/O rails to stabilize before their core rail is enabled, a common requirement in FPGA power sequencing datasheets specifying 1 ms to 10 ms inter-rail delay.
Can the LTC6994HS6-1#TRMPBF trigger on both rising and falling edges of the input signal?
Yes, the LTC6994HS6-1#TRMPBF supports selection of either rising or falling edge as the trigger for initiating the programmed delay. This flexibility allows it to delay both the assertion and de-assertion of a control signal, useful in applications like debounce circuits, motor brake timing, or watchdog reset pulses where both edges carry timing significance. The output polarity is true, meaning the output mirrors the input after the delay interval.
How does the SOT-23 package of the LTC6994HS6-1#TRMPBF compare to discrete RC delay implementations?
A discrete RC delay circuit requires a resistor, capacitor, and typically a Schmitt-trigger buffer to achieve comparable delay shaping, occupying more board area and suffering from timing accuracy limited by component tolerances of 5% or worse. The LTC6994HS6-1#TRMPBF in a 6-pin SOT-23 package integrates the timing oscillator and logic in a single 2.9 mm x 1.6 mm footprint, achieving better accuracy and requiring only one external resistor for delay programming from 1 µs to tens of seconds.
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About Analog Devices
Analog Devices (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing integrated circuits used in virtually all types of electronic equipment.
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|---|---|---|
| 19+ | $3.6400 | $69.16 |
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