EPM7128AETC100-10N Intel Integrated Circuit (Quad Flat Packages) In Stock
Intel EPM7128AETC100-10N is a MAX 7000AE CPLD with 128 macrocells, 84 I/O pins, 98 MHz max clock, and JTAG ISP support in a 100-pin TQFP package. Available from stock worldwide with fast shipping.
- Manufacturer
- Intel
- Package
- Quad Flat Packages
- Pin Count
- 100
- Lifecycle
- OBSOLETE
- Datasheet
- EPM7128AETC100-10N Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $42.2239(MOQ 5)
- Temp Range
- ?°C to 70.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 128 macrocells with 84 user I/O lines and 4 dedicated inputs for complex combinational and sequential logic
- Up to 98 MHz maximum clock frequency for high-speed glue logic and interface bridging applications
- In-system programmable (ISP) via JTAG boundary scan supporting fast design iteration without device removal
- 3.3 V core with 5 V-tolerant I/O pins enabling easy interfacing between mixed-voltage logic systems
Applications
The EPM7128AETC100-10N is used in digital glue logic, bus interface bridging, state machine implementation, and address decoding tasks in industrial controllers, telecommunications equipment, and embedded computing boards. Its 128 macrocells and 98 MHz clock speed make it suitable for protocol conversion and peripheral interface expansion in legacy and new FPGA-adjacent designs. The 100-pin TQFP package with JTAG ISP support simplifies in-field programming and board-level testing.
Specifications
| YTEOL | 0 |
| Additional Feature | YES |
| Clock Frequency-Max | 98MHz |
| In-System Programmable | YES |
| JESD-30 Code | S-PQFP-G100 |
| JESD-609 Code | e3 |
| JTAG BST | YES |
| Number of Dedicated Inputs | 4 |
| Number of I/O Lines | 84 |
| Number of Inputs | 92 |
| Number of Macro Cells | 128 |
| Number of Outputs | 84 |
| Organization | 4 DEDICATED INPUTS, 84 I/O |
| Output Function | MACROCELL |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | TQFP100,.63SQ |
| Package Shape | SQUARE |
| Package Style | FLATPACK, LOW PROFILE, FINE PITCH |
| Peak Reflow Temperature (Cel) | 260 |
| Programmable Logic Type | EE PLD |
| Propagation Delay | 10ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max | 3.6V |
| Supply Voltage-Min | 3V |
| Supply Voltage-Nom | 3.3V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | COMMERCIAL |
| Terminal Finish | Matte Tin (Sn) - annealed |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.5mm |
| Terminal Position | QUAD |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Quad Flat Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 3 |
| HTS Code | 8542.31.00.55 |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
How many macrocells and I/O pins does the EPM7128AETC100-10N provide?
The EPM7128AETC100-10N contains 128 macrocells and provides 84 user I/O lines along with 4 dedicated inputs, totaling 92 available inputs. This I/O count supports complex combinational and sequential logic design for bus interfacing, address decoding, and state machine applications in embedded systems.
What is the maximum operating frequency of the EPM7128AETC100-10N and does it support JTAG programming?
The EPM7128AETC100-10N supports a maximum clock frequency of 98 MHz and includes JTAG boundary scan (BST) for in-system programming and board-level testing. The -10N suffix denotes a 10 ns propagation delay grade, enabling high-speed glue logic and interface bridging without external programming hardware.
Which applications commonly use the EPM7128AETC100-10N in embedded system designs?
The EPM7128AETC100-10N is commonly used in digital glue logic, bus protocol conversion, peripheral address decoding, and state machine control circuits. With 128 macrocells operating at up to 98 MHz, it is well-suited for industrial automation controllers, telecommunications line cards, and embedded computing boards requiring flexible programmable logic.
What package does the EPM7128AETC100-10N use and is it suitable for compact board designs?
The EPM7128AETC100-10N is housed in a 100-pin TQFP (Thin Quad Flat Package) per JESD-30 code S-PQFP-G100. This square SMD package has a fine-pitch lead arrangement that allows 84 I/O pins and 4 dedicated inputs to be accessed in a relatively compact board footprint, suitable for space-constrained industrial and communications PCB designs.
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