CDP1802ACD3 Intersil Integrated Circuit (Ceramic Dual-In-Line Packages) In Stock
The CDP1802A/3 High-Reliability LSI CMOS 8-bit register oriented Central-Processing Unit (CPU) is designed for use as a general purpose computing or control element in a wide range of stored-program systems or products. The CDP1802A/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facilitate system design. The 1800 Series Architecture is desig
- Manufacturer
- Intersil
- Package
- Ceramic Dual-In-Line Packages
- Pin Count
- 40
- Lifecycle
- ACTIVE
- Datasheet
- CDP1802ACD3 Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- -55.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- Integrated Circuit from Intersil identified by manufacturer part number CDP1802ACD3
- Documented technical context includes 1802A for engineering comparison
- Package or mechanical reference recorded as Ceramic Dual-In-Line Packages for footprint checks
- Suitable for BOM sourcing, alternate review, repair stocking, and production procurement workflows
- Datasheet-backed context should be matched against voltage, current, timing, package, and lifecycle requirements before approval
Applications
CDP1802ACD3 is typically sourced for embedded electronics, industrial controls, communications equipment, and production BOM maintenance where buyers need a manufacturer-traceable integrated circuit with verifiable datasheet context. It is suitable for engineering replacement reviews, prototype builds, and production purchasing workflows that must confirm package fit, lifecycle risk, and key ratings such as 1802A.
Specifications
| Pbfree Code | Yes |
| Manufacturer Package Code | D40.6 |
| YTEOL | 4 |
| Address Bus Width | 8 |
| Bit Size | 8 |
| Boundary Scan | NO |
| Clock Frequency-Max | 3.6MHz |
| External Data Bus Width | 8 |
| Format | FIXED POINT |
| Integrated Cache | NO |
| JESD-30 Code | R-CDIP-T40 |
| JESD-609 Code | e4 |
| Low Power Mode | NO |
| Package Body Material | CERAMIC, METAL-SEALED COFIRED |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE |
| Qualification Status | Not Qualified |
| Speed | 3.6MHz |
| Supply Voltage-Max | 6.5V |
| Supply Voltage-Min | 4V |
| Supply Voltage-Nom | 5V |
| Surface Mount | NO |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | GOLD |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR |
| Package | Ceramic Dual-In-Line Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| ECCN | 3A001.a.2.c |
| HTS Code | 8542.31.00.15 |
| Country of Origin | USA |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
Which design checks should buyers confirm before selecting CDP1802ACD3?
Buyers should verify the integrated circuit role, package fit, lifecycle status, and datasheet ratings before approving this part. The fetched technical context includes 1802A, which should be matched against the target circuit and sourcing documentation.
How does the recorded package information affect sourcing CDP1802ACD3?
The recorded package reference is Ceramic Dual-In-Line Packages, so purchasers should confirm footprint compatibility, assembly handling, and approved manufacturer documentation. Include 1802A in the engineering review so procurement does not substitute a part with mismatched limits.
When comparing alternates for CDP1802ACD3, which parameters matter most?
Start with manufacturer, component category, package style, lifecycle status, and the electrical or mechanical ratings shown in the datasheet. Because the available context includes 1802A, any alternate should match that requirement before release.
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