CD74HC377PWRE4 Texas Instruments Integrated Circuit (Small Outline Packages) In Stock

CD74HC377PWRE4 is an 8-bit D-type flip-flop register from Texas Instruments in the HC/UH logic family, featuring a common clock enable (hold mode) for selective latching of 8 parallel data inputs. Operates at up to 20 MHz clock frequency with 4 mA output drive current and 50 pF load capacitance rating, suitable for data bus buffering and output port expansion. Available in automotive-grade TSSOP-20 tape-and-reel packaging for high-reliability production.

OBSOLETEIntegrated CircuitVerified Jun 2026
Package / Visual Reference
CD74HC377PWRE4Small Outline Packages
Quick Facts
Manufacturer
Texas Instruments
Package
Small Outline Packages
Pin Count
20
Lifecycle
OBSOLETE
Category
Integrated Circuit
Temp Range
-55.0°C to 125.0°C
RoHS
Compliant
Lead Time
3–7 business days
Shipping
DHL Express · Worldwide

What are the key features of CD74HC377PWRE4?

  • 8-bit parallel D flip-flop with common clock enable (hold mode) allows selective data capture without requiring external gating logic
  • 20 MHz maximum operating frequency with HC/UH family noise immunity suits medium-speed data bus and output latch applications
  • TSSOP-20 package with 4 mA output drive current (IOL) enables direct LED or bus line driving in space-constrained digital designs

What is CD74HC377PWRE4 used for?

The CD74HC377PWRE4 is used as an output port expander and data bus latch in microcontroller and FPGA peripheral designs, where 8 parallel data bits must be captured on a clock edge and held stable between updates. Its hold-mode clock enable is particularly useful in memory-mapped I/O architectures where the latch must retain its state while the data bus serves other devices, and the TSSOP-20 package saves board area in densely populated control boards.

What are the specifications of CD74HC377PWRE4?

YTEOL0
Additional FeatureWITH HOLD MODE
FamilyHC/UH
JESD-30 CodeR-PDSO-G20
JESD-609 Codee4
Load Capacitance (CL)50pF
Logic IC TypeD FLIP-FLOP
Max Frequency@Nom-Sup20000000Hz
Max I(ol)0.004A
Number of Bits8
Number of Functions1
Output PolarityTRUE
Package Body MaterialPLASTIC/EPOXY
Package Equivalence CodeTSSOP20,.25
Package ShapeRECTANGULAR
Package StyleSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Packing MethodTR
Peak Reflow Temperature (Cel)260
Power Supply Current-Max (ICC)0.16mA
Prop. Delay@Nom-Sup53ns
Propagation Delay (tpd)265ns
Qualification StatusNot Qualified
Supply Voltage-Max (Vsup)6V
Supply Voltage-Min (Vsup)2V
Supply Voltage-Nom (Vsup)5V
Surface MountYES
TechnologyCMOS
Temperature GradeMILITARY
Terminal FinishNICKEL PALLADIUM GOLD
Terminal FormGULL WING
Terminal Pitch0.65mm
Terminal PositionDUAL
Time@Peak Reflow Temperature-Max (s)30
Trigger TypePOSITIVE EDGE
fmax-Min23MHz
PackageSmall Outline Packages

Compliance & Regulatory

RoHS StatusCompliant
Lead-FreeYes (Pb-Free)
Moisture Sensitivity LevelMSL 1
HTS Code8542.39.00.60

Where can I find the CD74HC377PWRE4 datasheet?

CD74HC377PWRE4 Datasheet Download

Official datasheet from Texas Instruments

What are equivalent replacements for CD74HC377PWRE4?

Compatible alternatives and drop-in replacements for CD74HC377PWRE4:

CD74HC377PWTexas Instruments D

Flip-Flop, HC Series, 8-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

View Part →

Frequently Asked Questions

How does the clock enable (hold mode) of CD74HC377PWRE4 simplify output port design compared to a simple D flip-flop array?

The active-low clock enable (E) input on CD74HC377PWRE4 allows all 8 flip-flops to ignore clock edges when E is high, effectively freezing the output state without requiring external AND gates on each clock line. This built-in hold mode reduces the gate count and routing complexity in output port expander designs, saving at least one 8-input AND gate package and the associated propagation delay compared to gating the clock externally with a discrete 74HC08.

At 20 MHz operating frequency, what is the maximum propagation delay of CD74HC377PWRE4, and how does that affect timing margins?

CD74HC377PWRE4 is rated for up to 20 MHz at 50 pF load with a typical propagation delay of approximately 10 ns to 15 ns from clock rising edge to Q output at 5 V supply. In a 20 MHz system with a 50 ns clock period, this leaves roughly 35 ns of timing margin for setup and hold requirements of downstream logic, which is adequate for most 3.3 V and 5 V bus interfaces. Derate the maximum frequency to approximately 12 MHz at 3.3 V supply to maintain equivalent timing margins.

Can CD74HC377PWRE4 directly drive LEDs or resistive loads from its outputs at 4 mA current sink?

With a maximum output low current (IOL) of 4 mA, each output of CD74HC377PWRE4 can sink sufficient current to drive a standard LED with a 330-ohm series resistor from 5 V, resulting in approximately 10 mA forward current — which exceeds the 4 mA rated limit. For safe LED driving without exceeding IOL, use a 680-ohm to 1 kohm series resistor to limit sink current below 4 mA, or buffer the output with a dedicated LED driver capable of 20 mA to 40 mA per channel.

How does CD74HC377PWRE4 fit into a microcontroller output expansion design with address-decoded chip selects?

In an address-decoded output expansion scheme, the active-low write strobe from the microcontroller address decoder connects to the CD74HC377PWRE4 clock input, while the E pin ties to ground to always enable clocking. The 8 data bus lines connect to the D inputs, and the decoded chip select pulse latches the data into the flip-flops in a single 50 ns write cycle. Multiple CD74HC377PWRE4 devices can expand to 16, 24, or 32 parallel output bits by assigning each its own decode address, sharing the same 8-bit data bus.

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About Texas Instruments

Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.

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