CD74HC138EE4 Texas Instruments Integrated Circuit (Dual-In-Line Packages) In Stock
CD74HC138EE4 is a high-speed CMOS 3-to-8 line decoder and demultiplexer by Texas Instruments in the HC logic family. Key specs: 8 active-low outputs, 3 enable inputs for cascading, and a 2 V to 6 V supply range in a 16-pin PDIP package. Available from stock with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Dual-In-Line Packages
- Pin Count
- 16
- Lifecycle
- OBSOLETE
- Datasheet
- CD74HC138EE4 Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- -55.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of CD74HC138EE4?
- 3-to-8 line decoder with 8 active-low outputs and 3 enable inputs (2 active-low, 1 active-high) enabling direct cascade for larger address decode matrices
- High-speed CMOS HC family with 50 pF rated load capacitance and 4 mA output sink current, suitable for driving standard CMOS bus loads
- 2 V to 6 V wide supply range in a 16-pin PDIP package, compatible with 3.3 V and 5 V microcontroller address buses without external level shifting
What is CD74HC138EE4 used for?
The CD74HC138EE4 is used in microprocessor and microcontroller systems for memory address decoding, chip-select generation, and I/O port expansion where 3 address lines must select among up to 8 peripheral devices or memory banks. Its three enable inputs allow multiple CD74HC138 devices to be cascaded to decode 4-to-16 or larger address spaces without additional logic gates. The device is also applied as a 1-to-8 demultiplexer in data routing circuits, display drivers, and relay driver selector stages in industrial control systems.
What are the specifications of CD74HC138EE4?
| YTEOL | 0 |
| Family | HC/UH |
| Input Conditioning | STANDARD |
| JESD-30 Code | R-PDIP-T16 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | 3-LINE TO 8-LINE DECODER |
| Max I(ol) | 0.004A |
| Number of Bits | 8 |
| Number of Functions | 1 |
| Output Polarity | INVERTED |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | DIP16,.3 |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE |
| Packing Method | TUBE |
| Power Supply Current-Max (ICC) | 0.16mA |
| Prop. Delay@Nom-Sup | 30ns |
| Propagation Delay (tpd) | 225ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | NO |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| Package | Dual-In-Line Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.60 |
| Country of Origin | Malaysia, Mexico |
Where can I find the CD74HC138EE4 datasheet?
CD74HC138EE4 Datasheet DownloadOfficial datasheet from Texas Instruments
What are equivalent replacements for CD74HC138EE4?
Compatible alternatives and drop-in replacements for CD74HC138EE4:
Frequently Asked Questions
How does the CD74HC138EE4 decode a 3-bit binary address into 8 outputs and what do the enable pins do?
The CD74HC138EE4 takes a 3-bit binary select input (A0, A1, A2) and drives one of 8 active-low outputs (Y0–Y7) low while the remaining 7 outputs stay high. Three enable pins—two active-low (E1-bar, E2-bar) and one active-high (E3)—must all be satisfied simultaneously for decoding to occur; otherwise all 8 outputs remain high. This arrangement lets designers cascade multiple CD74HC138 devices to decode 4-bit or larger address busses using the enable pins as the higher-order address bit.
What supply voltage range does the CD74HC138EE4 support and how does it interface with 3.3 V microcontrollers?
The CD74HC138EE4 operates from 2 V to 6 V, covering both 3.3 V and 5 V logic systems. At 3.3 V supply, the input high threshold is approximately 2.3 V and the output drives at CMOS rail levels, making it directly compatible with 3.3 V microcontroller GPIO pins such as those on ARM Cortex-M or RISC-V devices without any level-shifter or resistor divider between the MCU and decoder.
Can two CD74HC138EE4 devices be cascaded to build a 4-to-16 decoder and how is the wiring done?
Yes, two CD74HC138EE4 devices can form a 4-to-16 decoder by connecting the 4th address bit to the E3 (active-high enable) pin of the first device and to E1-bar (active-low enable) of the second device. With E2-bar tied low on both, the first decoder is active when A3=0 and the second when A3=1, producing 16 mutually exclusive active-low chip-select lines from a 4-bit address bus with no additional logic gates required.
What is the propagation delay and output drive current of the CD74HC138EE4?
The CD74HC138EE4 has a typical propagation delay of approximately 13 ns at 4.5 V supply (VCC = 4.5 V, CL = 50 pF), making it fast enough for address decoding in systems with bus cycle times of 50 ns or longer. The output sink current rating is 4 mA, which is sufficient to drive standard CMOS inputs and LED indicators through a 220 Ω to 470 Ω current-limiting resistor in panel-indicator applications.
Is CD74HC138EE4 a direct drop-in substitute for the 74LS138 or 74HCT138 in existing PCB designs?
The CD74HC138EE4 shares the same pinout as the classic 74LS138 and is physically compatible with PDIP-16 footprints. However, its HC-family input thresholds are CMOS-referenced rather than TTL-referenced; if the driving logic uses TTL output levels (VOH as low as 2.4 V on a 5 V rail), the 74HCT138 variant with TTL-compatible inputs is the safer drop-in. In purely CMOS 3.3 V or 5 V systems, CD74HC138EE4 is a direct replacement with lower quiescent current than 74LS138.
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About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
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