CD74HC107MT Texas Instruments Integrated Circuit (Small Outline Packages) In Stock
CD74HC107MT is a dual negative-edge-triggered JK flip-flop in the HC CMOS family, with 2 independent elements clocked at up to 20 MHz in a 14-pin SOIC tape-and-reel package.
- Manufacturer
- Texas Instruments
- Package
- Small Outline Packages
- Pin Count
- 14
- Lifecycle
- OBSOLETE
- Datasheet
- CD74HC107MT Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.5832(MOQ 10)
- Temp Range
- -55.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of CD74HC107MT?
- Dual negative-edge-triggered JK flip-flop with independent J, K, clock, and asynchronous clear inputs per element
- 20 MHz maximum clock frequency at 5 V supply with 50 pF load drive for high-speed sequential logic designs
- HC CMOS technology provides 6 mA output sink current and 2 V to 6 V supply range for broad system compatibility
What is CD74HC107MT used for?
CD74HC107MT is used in digital frequency dividers, shift registers, and state machine designs where negative-edge clocking simplifies timing in synchronous logic boards operating at 2 V to 6 V. The 2 independent JK elements allow toggle-mode frequency division by 2, making it a compact prescaler for clock generation circuits in embedded systems. Its 14-pin SOIC surface-mount package in tape-and-reel format is suited for automated PCB assembly in consumer electronics and industrial control I/O boards.
What are the specifications of CD74HC107MT?
| YTEOL | 0 |
| Family | HC/UH |
| JESD-30 Code | R-PDSO-G14 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | J-K FLIP-FLOP |
| Max Frequency@Nom-Sup | 20000000Hz |
| Max I(ol) | 0.006A |
| Number of Bits | 2 |
| Number of Functions | 2 |
| Output Polarity | COMPLEMENTARY |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | SOP14,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE |
| Packing Method | TR |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 0.04mA |
| Prop. Delay@Nom-Sup | 51ns |
| Propagation Delay (tpd) | 255ns |
| Qualification Status | Not Qualified |
| Schmitt Trigger | NO |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Supply Voltage-Nom (Vsup) | 4.5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Terminal Form | GULL WING |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Trigger Type | NEGATIVE EDGE |
| fmax-Min | 24MHz |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.60 |
| Country of Origin | Malaysia |
Where can I find the CD74HC107MT datasheet?
CD74HC107MT Datasheet DownloadOfficial datasheet from Texas Instruments
What are equivalent replacements for CD74HC107MT?
Compatible alternatives and drop-in replacements for CD74HC107MT:
Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14
Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14
Frequently Asked Questions
At what supply voltage does CD74HC107MT achieve its 20 MHz maximum clock frequency?
CD74HC107MT achieves its 20 MHz maximum clock frequency at 5 V supply voltage, where HC CMOS propagation delays are shortest. At 3.3 V the achievable maximum clock rate drops to approximately 10 MHz to 15 MHz, and at 2 V supply it falls to around 2 MHz. For each of the 2 JK flip-flop elements, the 50 pF load capacitance specification applies at all voltages within the 2 V to 6 V operating range.
How does the asynchronous clear of CD74HC107MT behave in a digital counter reset circuit?
Each JK flip-flop in CD74HC107MT has an active-low asynchronous clear (CLR) input that immediately forces the Q output low independent of the clock signal. In a divide-by-2 counter, asserting CLR low for as little as the minimum pulse width of 10 ns at 5 V resets the flip-flop synchronously from the system perspective but without waiting for the next clock edge. This allows deterministic reset of 2-bit or cascaded multi-bit counters at power-on without relying on initial clock state.
For a PCB layout fitting 2 frequency divider stages in minimal board area, how does the 14-pin SOIC compare to a DIP package?
The 14-pin SOIC package of CD74HC107MT occupies approximately 8.65 mm × 3.9 mm on the PCB, roughly 4 times less footprint area than the equivalent 14-pin DIP at 19.1 mm × 6.35 mm. Both packages contain 2 JK flip-flop elements, so the SOIC version delivers the same 20 MHz clocking performance and 6 mA drive in a form factor compatible with modern high-density automated assembly lines using 0402 passive components nearby.
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Why Buy from FindMyChip
About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
More from Texas Instruments
| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 10+ | $0.9900 | $9.90 |
| 25+ | $0.8972 | $22.43 |
| 100+ | $0.7951 | $79.51 |
| 1000+ | $0.7807 | $780.70 |
| 10000+ | $0.6960 | $6960.00 |
| 100000+ | $0.5832 | $58320.00 |
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