CD74ACT280M Texas Instruments Integrated Circuit (Small Outline Packages) In Stock
The CD74ACT280M is a 9-bit odd/even parity generator and checker in ACT-family logic, capable of sink currents up to 75 mA per output and housed in a 14-pin SOIC package. It simultaneously provides both odd and even parity outputs for efficient error detection across 9 data bits. Available from major distributors with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Small Outline Packages
- Pin Count
- 14
- Lifecycle
- OBSOLETE
- Datasheet
- CD74ACT280M Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $0.4881(MOQ 100)
- Temp Range
- -55.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
What are the key features of CD74ACT280M?
- 9-bit simultaneous odd and even parity generation and checking in a single 14-pin SOIC device
- ACT-family TTL-compatible inputs operating at 5 V with propagation delays as low as 8 ns
- High output sink current of 75 mA enabling direct bus driving without additional buffers
- Cascadable architecture allowing expansion beyond 9-bit parity across wider data buses
What is CD74ACT280M used for?
The CD74ACT280M is used in data communication and memory subsystems requiring real-time error detection across 8-bit or 9-bit parallel data buses. Its dual odd/even outputs make it straightforward to implement both generating and checking functions in a single-chip solution for UART, memory, or backplane interfaces. It is also used in industrial control systems where data integrity verification over noisy signal lines is critical.
What are the specifications of CD74ACT280M?
| YTEOL | 0 |
| Additional Feature | ODD/EVEN PARITY GENERATOR |
| Family | ACT |
| JESD-30 Code | R-PDSO-G14 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | PARITY GENERATOR/CHECKER |
| Max I(ol) | 0.075A |
| Number of Bits | 9 |
| Number of Functions | 9 |
| Output Polarity | COMPLEMENTARY |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | SOP14,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE |
| Packing Method | TUBE |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 0.08mA |
| Prop. Delay@Nom-Sup | 19.6ns |
| Propagation Delay (tpd) | 21.6ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Terminal Form | GULL WING |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.60 |
| Country of Origin | Malaysia |
Where can I find the CD74ACT280M datasheet?
CD74ACT280M Datasheet DownloadOfficial datasheet from Texas Instruments
What are equivalent replacements for CD74ACT280M?
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
How does CD74ACT280M handle parity generation across more than 9 data bits?
To cover wider buses, multiple CD74ACT280M devices can be cascaded by connecting the even parity output of one stage to an input of the next. For example, two devices cover 17 data bits, providing a combined even parity output at ACT-level speeds with propagation delay approximately 16 ns end-to-end.
What output current capability does CD74ACT280M provide, and why does it matter for bus-drive designs?
The CD74ACT280M sinks up to 75 mA per output, which is more than double the 24 mA typical for standard HC-family logic. This allows the parity outputs to directly drive optocouplers, LEDs, or multi-load bus lines rated at 3.3 V to 5 V without intermediate buffer stages.
In a memory controller using CD74ACT280M, what is the typical parity check latency added to the data path?
With a 50 pF load at 5 V supply, CD74ACT280M propagation delay from any data input to the parity output is typically 8 ns. This sub-10 ns latency fits within the setup time budget of most SRAM and DRAM controllers running at 50 MHz to 100 MHz clock rates.
What are the physical dimensions of the CD74ACT280M SOIC-14 package for PCB footprint planning?
The CD74ACT280M uses the 14-pin SOIC package (R-PDSO-G14) with a body length of 8.65 mm, body width of 3.9 mm, and 1.27 mm lead pitch. Total land pattern width including leads is approximately 6 mm, compatible with standard SOIC-14 footprints in any EDA tool.
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Why Buy from FindMyChip
About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
More from Texas Instruments
| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 100+ | $0.6953 | $69.53 |
| 250+ | $0.6007 | $150.18 |
| 500+ | $0.5256 | $262.80 |
| 1000+ | $0.4881 | $488.10 |
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