CD74AC138M Texas Instruments Integrated Circuit (Small Outline Packages) In Stock
Texas Instruments CD74AC138M is a high-speed AC-logic 3-to-8 line decoder/demultiplexer with three enable inputs and 50 pF load drive capability in a 16-pin SOIC package. Suitable for address decoding and memory expansion in digital systems. Available in stock with worldwide shipping.
- Manufacturer
- Texas Instruments
- Package
- Small Outline Packages
- Pin Count
- 16
- Lifecycle
- OBSOLETE
- Datasheet
- CD74AC138M Datasheet PDF
- Category
- Integrated Circuit
- Temp Range
- -55.0°C to 125.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 3-to-8 line decoder with 2 active-low and 1 active-high enable inputs allowing cascaded enable logic without external gates
- AC-family CMOS logic operating at 2 V to 6 V with propagation delay under 10 ns enabling high-speed address decoding up to 100 MHz bus cycles
- 50 pF load drive capability in 16-pin SOIC package supporting direct connection to bus lines without buffer amplifiers
Applications
The CD74AC138M decodes 3-bit address buses into 8 individual chip-select lines in microprocessor memory systems, enabling the expansion of SRAM, Flash, or peripheral banks without additional glue logic. Its triple enable input structure allows direct connection to higher-order address bits and bus-request signals, reducing propagation delay in demultiplexed memory schemes operating at bus speeds up to 50 MHz. Embedded system designers also use it to drive relay arrays, LED matrices, and I/O port expanders where up to 8 independent output activations must be sequenced from a 3-line control bus.
Specifications
| YTEOL | 0 |
| Additional Feature | TWO ACTIVE-LOW AND ONE ACTIVE-HIGH ENABLE INPUTS |
| Family | AC |
| Input Conditioning | STANDARD |
| JESD-30 Code | R-PDSO-G16 |
| JESD-609 Code | e4 |
| Load Capacitance (CL) | 50pF |
| Logic IC Type | 3-LINE TO 8-LINE DECODER |
| Number of Bits | 8 |
| Number of Functions | 1 |
| Output Polarity | INVERTED |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | SOP16,.25 |
| Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE |
| Packing Method | TUBE |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supply Current-Max (ICC) | 0.16mA |
| Prop. Delay@Nom-Sup | 15.4ns |
| Propagation Delay (tpd) | 138ns |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 1.5V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | YES |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Terminal Form | GULL WING |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Package | Small Outline Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| Moisture Sensitivity Level | MSL 1 |
| ECCN | EAR99 |
| HTS Code | 8542.39.00.01 |
| Country of Origin | Malaysia, Mexico |
Alternate & Equivalent Parts
Compatible alternatives and drop-in replacements for CD74AC138M:
Frequently Asked Questions
How many output lines does the CD74AC138M decode from its 3-bit address input?
The CD74AC138M is a 3-to-8 line decoder, converting a 3-bit binary address at inputs A, B, and C into one of 8 active-low select outputs (Y0–Y7); each output drives up to 50 pF of load capacitance, covering most standard SRAM and Flash device input pins without external buffering.
What supply voltage range and propagation delay does the CD74AC138M offer in high-speed bus decoding?
The CD74AC138M AC-family device operates from 2 V to 6 V supply and achieves propagation delays below 10 ns at 5 V with a 50 pF load, enabling address decode cycles that fit within the setup-time budget of 50 MHz to 100 MHz microprocessor bus standards such as ISA and PC/104.
How do the three enable inputs of CD74AC138M simplify cascaded decoding systems?
The device provides two active-low enable inputs (E1-bar, E2-bar) and one active-high enable input (E3), so engineers can connect higher-order address lines directly to these pins without additional AND/OR gates, reducing the chip count in 4-to-16 or 5-to-32 decoder trees by at least one gate IC per stage.
When would a designer choose CD74AC138M over the older 74LS138 for the same address decoder function?
The CD74AC138M delivers propagation delays under 10 ns versus 22 ns for the 74LS138 at 5 V, draws less than 80 µA quiescent current versus up to 20 mA for the bipolar 74LS138, and operates down to 2 V making it compatible with 3.3 V FPGA I/O banks—these three advantages make it the preferred replacement whenever power budget is below 100 mW or bus speed exceeds 40 MHz.
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About Texas Instruments
Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.
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