CD4517BEE4 Texas Instruments Integrated Circuit (Dual-In-Line Packages) In Stock

CD4517BEE4 is a dual 64-stage static serial-in serial-out shift register with tapped outputs at the 16th, 32nd, 48th, and 64th stages, operating up to 3 MHz. It belongs to the 4000-series CMOS family in a 16-pin DIP package. Available from stock with worldwide shipping.

OBSOLETEIntegrated CircuitVerified May 2026
Package / Visual Reference
CD4517BEE4Dual-In-Line Packages
Quick Facts
Manufacturer
Texas Instruments
Package
Dual-In-Line Packages
Pin Count
16
Lifecycle
OBSOLETE
Category
Integrated Circuit
Temp Range
-55.0°C to 125.0°C
RoHS
Compliant
Lead Time
3–7 business days
Shipping
DHL Express · Worldwide

Key Features

  • Dual independent 64-stage shift register provides 128 total delay stages in a single 16-pin DIP, maximizing serial delay storage density
  • Intermediate taps at the 16th, 32nd, and 48th stages allow flexible delay selection without cascading multiple ICs
  • Static CMOS architecture retains register state indefinitely at zero clock frequency, enabling low-power pause in data-delay pipelines
  • 3 MHz maximum clock frequency and 50 pF load capacitance support standard 4000-series CMOS bus-speed serial data delay applications

Applications

CD4517BEE4 is used in serial data delay lines, digital echo circuits, and tapped delay implementations in audio signal processing and test equipment. Its dual 64-stage architecture with intermediate taps makes it suitable for programmable delay selection in BPSK bit synchronizers, frequency dividers, and sequencing circuits in industrial control logic. The 4000-series CMOS construction and wide 3V to 15V supply range support direct integration with both legacy TTL-compatible 5V boards and modern 3.3V microcontroller systems.

Specifications

Pbfree CodeYes
YTEOL0
Additional FeatureOUTPUTS ALSO AVAILABLE AT 16TH, 32ND AND 48TH STAGE OF THE SHIFT REGISTER
Count DirectionRIGHT
Family4000/14000/40000
JESD-30 CodeR-PDIP-T16
JESD-609 Codee4
Load Capacitance (CL)50pF
Logic IC TypeSERIAL IN SERIAL OUT
Max Frequency@Nom-Sup3000000Hz
Number of Bits64
Number of Functions2
Output Characteristics3-STATE
Output PolarityTRUE
Package Body MaterialPLASTIC/EPOXY
Package Equivalence CodeDIP16,.3
Package ShapeRECTANGULAR
Package StyleIN-LINE
Packing MethodTUBE
Peak Reflow Temperature (Cel)NOT SPECIFIED
Propagation Delay (tpd)400ns
Qualification StatusNot Qualified
Supply Voltage-Max (Vsup)18V
Supply Voltage-Min (Vsup)3V
Supply Voltage-Nom (Vsup)5V
Surface MountNO
TechnologyCMOS
Temperature GradeMILITARY
Terminal FinishNickel/Palladium/Gold (Ni/Pd/Au)
Terminal FormTHROUGH-HOLE
Terminal Pitch2.54mm
Terminal PositionDUAL
Time@Peak Reflow Temperature-Max (s)NOT SPECIFIED
Trigger TypePOSITIVE EDGE
fmax-Min8MHz
## CD4517BEE4 Alternates Showing resultsImage
PackageDual-In-Line Packages

Compliance & Regulatory

RoHS StatusCompliant
Lead-FreeYes (Pb-Free)
HTS Code8542.39.00.60

Datasheet

CD4517BEE4 Datasheet Download

Official datasheet from Texas Instruments

Alternate & Equivalent Parts

Compatible alternatives and drop-in replacements for CD4517BEE4:

Frequently Asked Questions

What intermediate tap outputs does CD4517BEE4 provide, and how do they help in programmable delay applications?

CD4517BEE4 provides data outputs at the 16th, 32nd, 48th, and 64th stages of each 64-stage shift register. At a 1 MHz clock these taps deliver delays of 16 µs, 32 µs, 48 µs, and 64 µs respectively, allowing a designer to select one of 4 delay steps from a single IC without cascading multiple devices or adding a multiplexer.

How does the static CMOS design of CD4517BEE4 benefit low-power delay-line applications?

The static CMOS architecture of CD4517BEE4 retains its 64-bit shift register state with no clock applied, drawing only leakage current in the nanoampere range when halted. This allows a system to freeze a data stream delay pipeline during sleep modes, saving the milliwatts that a dynamic shift register would consume refreshing state, making it practical for battery-powered instruments needing on-demand delay without power cycling the IC.

At what clock frequency does CD4517BEE4 operate, and what load capacitance should the designer plan for?

CD4517BEE4 is rated at a maximum clock frequency of 3 MHz with a nominal load capacitance of 50 pF per output. At 3 MHz the 64-stage register introduces a maximum propagation delay of approximately 21.3 µs end-to-end. Designers should limit PCB trace capacitance and fanout on the tap outputs to stay within the 50 pF load spec to achieve reliable timing at the full 3 MHz rate.

When would cascading two CD4517BEE4 devices be preferred over using a longer serial memory or FIFO for a 256-stage delay line?

Two CD4517BEE4 devices in cascade provide 256 total stages using only 32 pins across 2 through-hole DIP packages, which is lower cost and simpler to board-repair than a serial SRAM FIFO. For fixed-length audio echo delay applications below 3 MHz where the required delay length is a known multiple of 64 stages, the CD4517BEE4 cascade avoids the address and write-enable logic overhead of a FIFO, reducing gate count and PCB space in legacy CMOS 5V system designs.

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About Texas Instruments

Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.

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Lead Time3-7 business days
MOQFrom 1 piece
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OriginChina (Authorized)

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