74LVC16373ADGGR Texas Instruments Integrated Circuit (Small Outline Packages) In Stock

74LVC16373ADGGR is a 16-bit transparent D-type latch with 3-state outputs by Texas Instruments, operating from a 1.65 V to 3.6 V supply with outputs tolerant up to 5.5 V for mixed-voltage bus interfaces. The 48-pin TSSOP package provides two independently controlled 8-bit latch banks for address/data bus buffering. Available from stock with worldwide shipping.

ACTIVEIntegrated CircuitVerified Jun 2026
Package / Visual Reference
74LVC16373ADGGRSmall Outline Packages
Quick Facts
Manufacturer
Texas Instruments
Package
Small Outline Packages
Pin Count
48
Lifecycle
ACTIVE
Category
Integrated Circuit
RoHS
Compliant
Lead Time
3–7 business days
Shipping
DHL Express · Worldwide

What are the key features of 74LVC16373ADGGR?

  • 16 D-type latches organized as dual 8-bit banks with independent output enables, supporting simultaneous or split-bank data latching on 16-bit parallel buses
  • 3-state outputs with 5.5 V bus-hold tolerance on a 1.65 V to 3.6 V supply, enabling direct interfacing between 3.3 V logic and legacy 5 V bus systems without level-shift logic
  • LVC-series CMOS technology with propagation delay below 4 ns at 3.3 V and output drive of ±24 mA, suitable for high-speed address/data bus latching in embedded processors and FPGAs

What is 74LVC16373ADGGR used for?

The 74LVC16373ADGGR is used in microprocessor and FPGA memory bus designs as a 16-bit address latch or data bus buffer, demultiplexing address and data from multiplexed address/data buses at data rates up to 200 MHz. Its 5 V tolerant inputs allow the LVC device to bridge between a 3.3 V processor and 5 V SRAM or peripheral ICs without additional translation hardware. It also suits PCI bus buffering, I/O expansion for embedded controllers, and parallel data capture in high-density industrial control boards.

Compliance & Regulatory

RoHS StatusCompliant
Lead-FreeYes (Pb-Free)

Where can I find the 74LVC16373ADGGR datasheet?

74LVC16373ADGGR Datasheet Download

Official datasheet from Texas Instruments

What are equivalent replacements for 74LVC16373ADGGR?

Compatible alternatives and drop-in replacements for 74LVC16373ADGGR:

SN74LVC16373ADGVRTexas Instruments

Bus Driver, LVC/LCX/Z Series, 16-Func, 8-Bit, True Output, CMOS, PDSO48

View Part →

Frequently Asked Questions

What supply voltage range does the 74LVC16373ADGGR operate from, and can its outputs directly interface with 5 V logic without damage?

The 74LVC16373ADGGR operates from 1.65 V to 3.6 V and its inputs and outputs are tolerant of bus voltages up to 5.5 V. This means 5 V logic can drive the inputs directly, and the 3-state outputs can be connected to a 5 V bus without damage, enabling seamless voltage translation between a 3.3 V processor and legacy 5 V peripheral ICs in mixed-supply system designs.

How does the dual 8-bit bank organization of the 74LVC16373ADGGR help in address/data bus demultiplexing for microcontrollers with multiplexed buses?

The 74LVC16373ADGGR's 16 latches are organized in two independently gated 8-bit groups, each with its own output-enable pin. In a multiplexed address/data bus, the lower 8-bit bank can latch the address on the falling edge of the ALE signal while the upper 8-bit bank handles the data, allowing both halves of the bus to be captured independently within the same 48-pin TSSOP package — saving a second latch IC compared to two 8-bit 74LVC373 devices.

What propagation delay does the 74LVC16373ADGGR achieve at 3.3 V, and what is its output drive capability?

At a 3.3 V supply, the 74LVC16373ADGGR achieves a typical propagation delay of approximately 3.5 ns to 4 ns from latch input to output. Each output can sink or source up to 24 mA, which is sufficient to drive standard CMOS bus loads and short PCB traces at signal frequencies up to 200 MHz, making it suitable for high-speed parallel bus interfaces in embedded processors and FPGA-based data acquisition systems.

How many independent output-enable controls does the 74LVC16373ADGGR provide, and how does this benefit multi-master bus architectures?

The 74LVC16373ADGGR has 2 independent active-low output-enable pins, one for each 8-bit group of 8 latches. In a multi-master or shared bus architecture, each enable can be asserted separately to place either byte-wide bank in high-impedance 3-state mode, preventing bus contention when another master drives the same 16-bit bus. This independent control eliminates the need for additional bus-switch ICs in 16-bit wide shared memory or I/O bus designs.

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About Texas Instruments

Texas Instruments (TI) is a global semiconductor company headquartered in Dallas, Texas. TI designs and manufactures analog and embedded processing chips used in industrial, automotive, consumer, communications, and enterprise systems.

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OriginChina (Authorized)

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