25LC256-I/P Microchip Integrated Circuit (Dual-In-Line Packages) In Stock
25LC256-I/P is a 256 Kbit (32 KB) SPI serial EEPROM from Microchip supporting clock frequencies up to 10 MHz and over 1,000,000 write/erase cycles. It offers a minimum 200-year data retention rating and operates in an 8-pin DIP package, ideal for non-volatile data storage in embedded systems.
- Manufacturer
- Microchip
- Package
- Dual-In-Line Packages
- Pin Count
- 8
- Lifecycle
- ACTIVE
- Datasheet
- 25LC256-I/P Datasheet PDF
- Category
- Integrated Circuit
- Price
- From $1.2200(MOQ 1)
- Temp Range
- -40.0°C to 85.0°C
- RoHS
- Compliant
- Lead Time
- 3–7 business days
- Shipping
- DHL Express · Worldwide
Key Features
- 256 Kbit (32 KB) total storage capacity organized as 512 pages of 64 bytes each
- SPI serial interface supporting up to 10 MHz clock for fast data transfers
- Endurance of 1,000,000 write/erase cycles per memory location for long service life
- Data retention minimum of 200 years ensuring reliable non-volatile storage
- 8-pin DIP package for straightforward through-hole or adapter-based prototyping
- Low-power CMOS design compatible with 2.5 V to 5.5 V supply voltages
Applications
The 25LC256-I/P is used for non-volatile configuration storage, calibration data retention, and firmware parameter saving in microcontroller-based systems where data must persist through power cycles. Its 32 KB capacity is well-suited for storing user settings, sensor calibration tables, and event logs in industrial instruments, smart meters, and consumer electronics. The SPI interface at up to 10 MHz enables fast read/write access from most 8-bit and 32-bit microcontrollers with minimal firmware overhead.
Specifications
| Pbfree Code | Yes |
| Manufacturer Package Code | PDIP-8 |
| Factory Lead Time | 8Weeks |
| YTEOL | 8 |
| Clock Frequency-Max (fCLK) | 10MHz |
| Data Retention Time-Min | 200 |
| Endurance | 1000000 Write/Erase Cycles |
| JESD-30 Code | R-PDIP-T8 |
| JESD-609 Code | e3 |
| Memory Density | 262144bit |
| Memory IC Type | EEPROM |
| Memory Width | 8 |
| Number of Functions | 1 |
| Number of Ports | 1 |
| Number of Words | 32768words |
| Number of Words Code | 32000 |
| Operating Mode | SYNCHRONOUS |
| Organization | 32KX8 |
| Output Characteristics | 3-STATE |
| Package Body Material | PLASTIC/EPOXY |
| Package Equivalence Code | DIP8,.3 |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE |
| Parallel/Serial | SERIAL |
| Programming Voltage | 2.5V |
| Qualification Status | Not Qualified |
| Reverse Pinout | NO |
| Screening Level | AEC-Q100 |
| Serial Bus Type | SPI |
| Standby Current-Max | 0.000001A |
| Supply Current-Max | 0.006mA |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2.5V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | NO |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| Write Cycle Time-Max (tWC) | 5ms |
| Write Protection | HARDWARE/SOFTWARE |
| Package | Dual-In-Line Packages |
Compliance & Regulatory
| RoHS Status | Compliant |
| Lead-Free | Yes (Pb-Free) |
| ECCN | EAR99 |
| HTS Code | 8542.32.00.51 |
| Country of Origin | Thailand |
Alternate & Equivalent Parts
No known alternates. Submit an RFQ and our team can suggest alternatives.
Frequently Asked Questions
What is the storage capacity and page organization of the 25LC256-I/P EEPROM?
The 25LC256-I/P provides 256 Kbit of storage, equivalent to 32 KB, organized as 512 pages of 64 bytes each. Page writes allow up to 64 bytes to be programmed in a single SPI write cycle, significantly improving throughput for block data operations compared to byte-at-a-time programming.
How many write cycles does the 25LC256-I/P support, and is it suitable for frequently updated data logs?
The 25LC256-I/P is rated for a minimum of 1,000,000 write/erase cycles per address location, which at a rate of 1 write per second equates to over 11 days of continuous updates per cell. For event logs written at 1 Hz to rotating address blocks across 32 KB, wear-leveling extends effective lifetime to years of reliable operation.
At what maximum SPI clock speed can the 25LC256-I/P operate, and how quickly can a full 32 KB read be completed?
The 25LC256-I/P supports SPI clock frequencies up to 10 MHz, enabling a full sequential read of its 32 KB (262,144 bits) in approximately 26 ms at maximum speed. This is fast enough for startup configuration loads, calibration table reads, or firmware parameter restores in virtually any embedded application.
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| Qty. | Unit Price | Ext. Price |
|---|---|---|
| 1+ | $1.2200 | $1.22 |
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