Integrated Circuit

SC-88A

Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Designed for 1.65 V to 5.5 V Vcc Operatio; High Speed: tPD = 3.5ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Power Down Protection Provided on Inputs; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available

Designed for 1.65 V to 5.5 V Vcc Operatio; High Speed: tPD = 3.5ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Power Down Protection Provided on Inputs; Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available

Wide Operating Vcc Range; High Speed: tPD = 3.5ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Power Down Protection Provided on Inputs; Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available

TSOP-5

Low Internal Power Dissipation: ICC = 1µA (Max) at TA = 25°C; High Speed: tPD = 4.3ns (Typ) at VCC = 5V; Power Down Protection Provided on Inputs; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = <100; Pb-Free Packages are Available; Designed for 2.0 V to 5.5 V VCC Operation

Designed for 2.0 V to 5.5 V VCC Operation; Low Power Dissipation: ICC = 1.0 µA (Max) at TA = 25°C; High Speed: tPD = 3.7ns (Typ) at VCC = 5V; Power Down Protection Provided on Inputs; Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available

Designed for 2.0 V to 5.5 V VCC Operation; Low Power Dissipation: ICC = 1.0 µA (Max) at TA = 25°C; High Speed: tPD = 3.7ns (Typ) at VCC = 5V; Power Down Protection Provided on Inputs; Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available

High Speed: tPD = 3.5ns (Typ) at VCC = 5V; Balanced Propagation Delays; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available; Designed for 2.0 V to 5.5 V Vcc Operation; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Power Down Protection Provided on Inputs; Pin and Function Compatible with Other Standard Logic Families

Pin and Function Compatible with Other Standard Logic Families; Balanced Propagation Delays; High Speed: tPD = 3.5ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Power Down Protection Provided on Inputs; Designed for 2.0 V to 5.5 V VCC Operation; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available

Power Down Protection Provided on Inputs; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FET = <100; Designed for 2.0 V to 5.5 V Vcc Operation Wide Operating Vcc Range; High Speed: tPD = 3.8ns (Typ) at VCC = 5V; Low Internal Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Pb-Free Packages are Available

Wide Operating Vcc Range; High Speed: tPD = 3.5ns (Typ) at VCC = 5V; Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Power Down Protection Provided on Inputs; Balanced Propagation Delays; Pin and Function Compatible with Other Standard Logic Families; Chip Complexity: FETs = ≤ 100; Pb-Free Packages are Available

Pin and Function Compatible with Other Standard Logic Families; Latchup Performance Exceeds 300mA; Designed for 2V to 5.5V Operating Range; Low Noise: VOLP = 0.8 V (Max); ESD Performance: HBM > 2000V; Machine Model > 200V; Chip Complexity: 122 FETs or 30.5 Equivalent Gates; Balanced Propagation Delays; High Speed: tPD = 5.7ns (Typ) at VCC = 5V; Power Down Protection Provided on Inputs; High Noise Immunity: VNIH = VNIL = 28% VCC; Low Power Dissipation: ICC = 4mA (Max) at TA = 25°C; These devices are availabl

Low Power Dissipation: ICC = 2µA (Max) at TA = 25 C; Balanced Propagation Delays; High Speed: tPD = 4.9ns (Typ) at VCC = 5V; Pin and Function Compatible with Other Standard Logic Families; Power Down Protection Provided on Inputs; Low Noise: VOLP = 0.8V (Max); High Noise Immunity: VNIH = VNIL = 28% VCC; Designed for 2V to 5.5V Operating Range; Chip Complexity: 72 FETs or 18 Equivalent Gates; ESD Performance: HBM > 2000V; Machine Model > 200V; Latchup Performance Exceeds 300mA; Pb-Free Packages are Available

Latchup Performance Exceeds 300mA; High Speed: tPD = 4.1ns (Typ) at VCC = 5V; Balanced Propagation Delays; Power Down Protection Provided on Inputs; Chip Complexity: 82 FETs or 20 Equivalent Gates; Pin and Function Compatible with Other Standard Logic Families; ESD Performance: HBM > 2000V; Machine Model > 200V; High Noise Immunity: VNIH = VNIL = 28% VCC; Low Noise: VOLP = 0.8V (Max); Designed for 2V to 5.5V Operating Range; Low Power Dissipation: ICC = 4mA (Max) at TA = 25°C; These devices are available in

Power Down Protection Provided on Inputs; High Speed: tPD = 3.7ns (Typ) at VCC = 5V; Low Internal Power Dissipation: ICC = 1µA (Max) at TA = 25°C; Pin and Function Compatible with Other Standard Logic Families; Designed for 2.0 V to 5.5 V Vcc Operation Wide Operating Vcc Range; Chip Complexity: FETs = <100; Pb-Free Packages are Available

Designed for 2V to 5.5V Operating Range; High Noise Immunity: VNIH = VNIL = 28% VCC; High Speed: tPD = 5.5ns (Typ) at VCC = 5V; Balanced Propagation Delays; Chip Complexity: 60 FETs or 15 Equivalent Gates; Low Noise: VOLP = 0.8V (Max); Low Power Dissipation: ICC = 2µA (Max) at TA = 25 C; Latchup Performance Exceeds 300mA; ESD Performance: HBM > 2000 V; Machine Model > 200 V; Pin and Function Compatible with Other Standard Logic Families; Power Down Protection Provided on Inputs; Pb-Free Packages are Availab

Low Noise; Analog Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; Low Crosstalk Between Switches; In Compliance With the Requirements of JEDEC Standard No. 7A; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Fast Switching and Propagation Speeds; Diode Protection on All Inputs/Outputs; Pb-Free Packages are Available*

Bidirectional Interface Between 3V and 3V/5V Buses; Flexible VCCB Operating Range; Available in SOIC and TSSOP Packages; Functionally Compatible with the 74 Series 245 PIN Pins OE T/R A0-A7 B0-B7; Outputs Source/Sink Up to 24mA; Control Inputs Compatible with TTL Level; Allows B Port and VCCB to Float Simultaneously When OE Is High; Guaranteed Simultaneous Switching Noise Level and Dynamic Threshold Performance; Pb-Free Packages are Available*

Designed to Operate on a Single Supply with VEE = GND, or UsingSplit Supplies up to +/- 3.0 V; Low Noise; Fast Switching and Propagation Speeds; Improved Linearity and Lower ON Resistance than Metal-Gate, HSL, or VHC Counterparts; Digital (Control) Power Supply Range (VCC - GND) = 2.5 to 6.0 V; Analog Power Supply Range (VCC - VEE) = -3.0 V to +3.0 V; Low Crosstalk Between Switches; Select Pins Compatible with TTL Levels; Break-Before-Make Circuitry; Pb-Free Packages are Available*

Chip Complexity: LVX8053 - 156 FETs or 39 Equivalent Gates; Analog Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Fast Switching and Propagation Speeds; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Low Noise; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; Diode Protection on All Inputs/Outputs; Low Crosstalk Between Switches; In Compliance With the Requirements of JEDEC Standard No. 7A; Pb-Free Packages are Available*

Low Noise: VOLP = 0.8V (Max); Power Down Protection Provided on Inputs; ESD Performance: HBM > 2000V; Machine Model > 200V; High Noise Immunity: VNIH = VNIL = 28% VCC; Low Power Dissipation: ICC = 2µA (Max) at TA = 25 C; High Speed: tPD = 3.8ns (Typ) at VCC = 5V; Pin and Function Compatible with Other Standard Logic Families; Designed for 2V to 5.5V Operating Range; Latchup Performance Exceeds 300mA; Balanced Propagation Delays; Chip Complexity: 36 FETs or 9 Equivalent Gates; These devices are available in

Bidirectional Interface Between 3V and 3V/5V Buses; Flexible VCCB Operating Range; Available in SOIC and TSSOP Packages; Functionally Compatible with the 74 Series 245 PIN Pins OE T/R A0-A7 B0-B7; Outputs Source/Sink Up to 24mA; Control Inputs Compatible with TTL Level; Allows B Port and VCCB to Float Simultaneously When OE Is High; Guaranteed Simultaneous Switching Noise Level and Dynamic Threshold Performance; Pb-Free Packages are Available*

Chip Complexity: 100 FETs or 29 Equivalent Gates; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Output Drive Capability: 10 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS and TTL; Low Input Current: 1.0 mA; High Noise Immunity Characteristic of CMOS Devices; Operating Voltage Range: 2.0 to 6.0 V; Pb-Free Packages are Available*

Designed to Operate on a Single Supply with VEE = GND, or Using Split Supplies up to +/- 3.3 V; Analog Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Low Noise; Low Crosstalk Between Switches; Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts; Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V; Fast Switching and Propagation Speeds; Pb-Free Packages are Available

Near Zero Static Supply Current in All Three Logic States (10mA) Substantially Reduces System Power Requirements; 24mA Balanced Output Sink and Source Capability; LVCMOS Compatible; IOFF Specification Guarantees High Impedance When VCC = 0V; ESD Performance: Human Body Model >2000V; Machine Model >200V; 5V Tolerant - Interface Capability With 5V TTL Logic; Designed for 2.3 to 3.6V V CC Operation; Supports Live Insertion and Withdrawal; LVTTL Compatible; Latchup Performance Exceeds 500mA; Pb-Free Packages ar

IOFF Specification Guarantees High Impedance When VCC = 0V; 5V Tolerant - Interface Capability With 5V TTL Logic; Near Zero Static Supply Current in All Three Logic States (10µA) Substantially Reduces System Power Requirements; Designed for 2.3 to 3.6V VCC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; Latchup Performance Exceeds 500mA; Supports Live Insertion and Withdrawal; 24mA Balanced Output Sink and Source Capability; LVTTL Compatible; LVCMOS Compatible; Pb-Free Packages are

Latchup Performance Exceeds 300mA; High Speed: tPD = 5.1ns (Typ) at VCC = 3.3V; Low Power Dissipation: ICC = 4µA (Max) at TA = 25 C; Low Noise: VOLP = 0.5V (Max); ESD Performance: HBM > 2000V; Machine Model > 200V; Power Down Protection Provided on Inputs; Pin and Function Compatible with Other Standard Logic Families; Balanced Propagation Delays; Pb-Free Packages are Available*

Balanced Propagation Delays; Low Noise: VOLP = 0.5V (Max); Power Down Protection Provided on Inputs; ESD Performance: HBM > 2000V; Machine Model > 200V; Low Power Dissipation: ICC = 4µA (Max) at TA = 25 C; High Speed: tPD = 4.4ns (Typ) at VCC = 3.3V; Pin and Function Compatible with Other Standard Logic Families; Latchup Performance Exceeds 300mA; Pb-Free Packages are Available*

TSSOP-14

Low Noise: VOLP = 0.5V (Max); Latchup Performance Exceeds 300mA; Power Down Protection Provided on Inputs; ESD Performance: HBM > 2000V; Machine Model > 200V; Low Power Dissipation: ICC = 2µA (Max) at TA = 25 C; High Speed: tPD = 4.8ns (Typ) at VCC = 3.3V; Pin and Function Compatible with Other Standard Logic Families; Balanced Propagation Delays; Pb-Free Packages are Available*

LVTTL Compatible; Designed for 2.7 to 3.6V V CC Operation; Near Zero Static Supply Current in All Three Logic States (10mA) Substantially Reduces System Power Requirements; 24mA Balanced Output Sink and Source Capability; Latchup Performance Exceeds 500mA; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; ESD Performance: Human Body Model >2000V; Machine Model >200V; Pb-Free Packages are Available*

5V Tolerant - Interface Capability With 5V TTL Logic; LVTTL Compatible; Supports Live Insertion and Withdrawal; IOFF Specification Guarantees High Impedance When VCC = 0V; LVCMOS Compatible; ESD Performance: Human Body Model >2000V;Machine Model >200V; Near Zero Static Supply Current in All Three Logic States (20mA) Substantially Reduces System Power Requirements; Latchup Performance Exceeds 500mA; 24mA Balanced Output Sink and Source Capability; 4.5ns Maximum tpd; Designed for 2.3 to 3.6V VCC Operation; Th

Latchup Performance Exceeds 500mA; Supports Live Insertion and Withdrawal; Designed for 2.3 to 3.6V VCC Operation; LVCMOS Compatible; 5V Tolerant - Interface Capability With 5V TTL Logic; 24mA Balanced Output Sink and Source Capability; ESD Performance: Human Body Model >2000V; Machine Model >200V; Near Zero Static Supply Current in All Three Logic States (10mA) Substantially Reduces System Power Requirements; IOFF Specification Guarantees High Impedance When VCC = 0V; LVTTL Compatible; Pb-Free Packages are

LVTTL Compatible; Supports Live Insertion and Withdrawal; ESD Performance: Human Body Model >2000V; Machine Model >200V PIN; 24mA Balanced Output Sink and Source Capability; Near Zero Static Supply Current in All Three Logic States (10µA) Substantially Reduces System Power Requirements; Designed for 2.0 to 5.5V VCC Operation; Latchup Performance Exceeds 500mA; LVCMOS Compatible; 5V Tolerant Interface Capability With 5V TTL Logic; IOFF Specification Guarantees High Impedance When VCC = 0V; Pb-Free Packages

Pin and Function Compatible with Other Standard Logic Families; Power Down Protection Provided on Inputs; Low Noise: VOLP = 0.5V (Max); Low Power Dissipation: ICC = 4µA (Max) at TA = 25 C; Latchup Performance Exceeds 300mA; ESD Performance: HBM > 2000V; Machine Model > 200V PIN; High Speed: tPD = 5.5ns (Typ) at VCC = 3.3V; Balanced Propagation Delays; Pb-Free Packages are Available*

LVTTL Compatible; Supports Live Insertion and Withdrawal; ESD Performance: Human Body Model >2000V; Machine Model >200V PIN; 24mA Balanced Output Sink and Source Capability; Near Zero Static Supply Current in All Three Logic States (10µA) Substantially Reduces System Power Requirements; Designed for 2.0 to 5.5V VCC Operation; Latchup Performance Exceeds 500mA; LVCMOS Compatible; 5V Tolerant Interface Capability With 5V TTL Logic; IOFF Specification Guarantees High Impedance When VCC = 0V; Pb-Free Packages

Near Zero Static Supply Current in All Three Logic States (10mA) Substantially Reduces System Power Requirements; 24mA Balanced Output Sink and Source Capability; LVCMOS Compatible; IOFF Specification Guarantees High Impedance When VCC = 0V; ESD Performance: Human Body Model >2000V; Machine Model >200V; 5V Tolerant - Interface Capability With 5V TTL Logic; Designed for 2.3 to 3.6V V CC Operation; Supports Live Insertion and Withdrawal; LVTTL Compatible; Latchup Performance Exceeds 500mA; Pb-Free Packages ar

5V Tolerant Inputs - Interface Capability With 5V TTL Logic; LVCMOS Compatible; Designed for 2.3 to 3.6V V CC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; Latchup Performance Exceeds 500mA; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; LVTTL Compatible; 24mA Balanced Output Sink and Source Capability; Pb-Free Packages are Available*

Designed for 2.7 to 3.6V VCC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; LVTTL Compatible; 24mA Balanced Output Sink and Source Capability; Latchup Performance Exceeds 500mA; Pb-Free Packages are Available*

5V Tolerant Inputs - Interface Capability With 5V TTL Logic; ESD Performance: Human Body Model >2000V; Machine Model >200V; Latchup Performance Exceeds 500mA; Near Zero Static Supply Current (10µA) Substantially Reduces System Power Requirements; LVCMOS Compatible; Designed for 2.3 to 3.6V VCC Operation; 24mA Balanced Output Sink and Source Capability; LVTTL Compatible; Pb-Free Packages are Available*

5V Tolerant Inputs - Interface Capability With 5V TTL Logic; LVTTL Compatible; 24mA Balanced Output Sink and Source Capability; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; Designed for 2.3 V to 3.6 V VCC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; Latchup Performance Exceeds 500mA; LVCMOS Compatible; Pb-Free Packages are Available*

Output Drive Capability: 15 LSTTL Loads; TTL NMOS-Compatible Input Levels; Outputs Directly Interface to CMOS, NMOS, and TTL; Operating Voltage Range: 4.5 to 5.5 V; Low Input Current: 1 mA; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 112 FETs or 28 Equivalent Gates; Pb-Free Packages are Available

Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; ESD Performance: Human Body Model >2000V; Machine Model >200V; Designed for 2.3V to 3.6V VCC Operation; Latchup Performance Exceeds 500mA; LVTTL Compatible; LVCMOS Compatible; 24mA Balanced Output Sink and Source Capability; Pb-Free Packages are Available*

In Compliance with the Requirements Defined by JEDEC Standard No. 7A; TTL/NMOS-Compatible Input Levels; Chip Complexity: 72 FETs or 18 Equivalent Gates; Operating Voltage Range: 4.5 to 5.5 V; Output Drive Capability: 10 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS and TTL; Low Input Current: 1.0 mA; Pb-Free Packages are Available

LVCMOS Compatible; ESD Performance: Human Body Model >1500V; Machine Model >200V; 5 V Tolerant Inputs/Outputs; LVTTL Compatible; 24mA Output Sink Capability; Designed for 2.3 to 5.5 V VCC Operation; Latchup Performance Exceeds 500mA; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; Wired-OR, Wired-AND; Output Can Be Set Externally Without Affecting Speed or Device; Pb-Free Packages are Available*

Designed for 2.7 to 3.6V VCC Operation; ESD Performance: Human Body Model >2000V; Machine Model >200V; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; LVTTL Compatible; 24mA Balanced Output Sink and Source Capability; Latchup Performance Exceeds 500mA; Pb-Free Packages are Available*

Output Drive Capability: 10 LSTTL Loads; High Noise Immunity Characteristic of CMOS Devices; Outputs Directly Interface to CMOS, NMOS, and TTL; Low Input Current: 1 mA; Chip Complexity: 12 FETs or 3 Equivalent Gates; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator Configurations; Pb-Free Packages are Available

ESD Performance: Human Body Model >2000V; Machine Model >200V; Near Zero Static Supply Current (10mA) Substantially Reduces System Power Requirements; 24mA Balanced Output Sink and Source Capability; Designed for 2.3 to 3.6V VCC Operation; LVCMOS Compatible; Latchup Performance Exceeds 500mA; 5V Tolerant Inputs - Interface Capability With 5V TTL Logic; LVTTL Compatible

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