5V Logic Meets 3.3V IoT: Selecting Between SN74HC02, HCT and LVC NOR Gates

Bottom Line: When mixing a 5V legacy domain with 3.3V (or lower) IoT MCUs, three parameters decide which NOR gate you should specify: input-threshold compatibility with your driving rail, supply-voltage range across the rest of the board, and propagation delay at your switching frequency. For a 5V-only design, the SN74HC02 quad NOR remains the workhorse. To accept a 3.3V signal on a 5V rail without external level shifting, the HCT-family equivalent is the cheapest single-chip fix. For sub-3.3V battery-powered nodes, an AUC- or LVC-family single-gate NOR is the only correct choice. The next 2,000 words show how to pick between them with concrete numbers, not folklore.

Why one logic family no longer fits every board

Ten years ago a hardware engineer prototyping with a 5V MCU could populate every glue-logic footprint with HC-family parts and ship. Today an "IoT product" usually mixes a 3.3V Wi-Fi/BLE module, a 1.8V or 3.3V sensor cluster, and a residual 5V rail driving relays, displays, or motor predrivers. NOR gates sit at the seams between those domains, and choosing the wrong family is the single most common cause of intermittent boot failures and missed-edge bugs that only show up at temperature corners.

The Texas Instruments 74-series logic catalog now spans seven families that all happen to publish a xx02 quad NOR variant: HC, HCT, AC, ACT, AHC, AHCT, AUC, ALVC, LVC, LV, and AUP among them. The differences that matter for selection are summarized below.

Key Selection Parameters

1. Input switching threshold (V_IH/V_IL)

This is the parameter that decides whether your gate even sees a logic-1 from your MCU. HC-family inputs use CMOS thresholds — V_IH is 70% of V_CC, so on a 5V rail the gate needs at least 3.5V to register a high. A 3.3V GPIO swinging to 3.0–3.2V under load will be misread as undefined.

HCT-family inputs use TTL thresholds (V_IH = 2.0V on a 5V rail), so the same 3.3V GPIO is read cleanly. AHC/AHCT raise the drive strength but keep the same threshold philosophy. AUC and LVC drop the entire rail to 1.65–3.6V, so threshold compatibility falls out for free.

Selection rule: if your driver and gate sit on different rails, do not use HC. Use HCT for 5V supply with 3.3V drive, or use a 1.65–5.5V part such as the LVC family.

2. Supply voltage range (V_CC)

HC and HCT are nominally 2–6V, but datasheet AC parameters are guaranteed only at 4.5V and 5V. AHC widens the same to 2–5.5V with full guarantees down to 2V. AUC operates at 0.8–2.7V, which is the family's reason to exist for 1.0V/1.2V battery designs.

The trap: a 3.3V rail on an HC quad NOR works, but propagation delay rises from 9 ns at 5V to 24 ns at 2V (typical). If your timing budget assumed datasheet headline numbers, the part will appear "slow" simply because it is being run off a low rail.

3. Propagation delay (t_PD)

For switching-edge applications — clock gating, debounce circuits, edge detectors — t_PD drives the maximum operating frequency. Indicative numbers at room temperature:

HC quad NOR at 5V — 7–12 ns
HCT quad NOR at 5V — 9–14 ns (the level-shifting input stage costs ~2 ns)
AHC at 5V — 5.5 ns
AUC single-gate NOR at 1.8V — 2.5 ns
LVC at 3.3V — 2.5–4 ns

If you are sampling 1 MHz signals, any family works. At 50–100 MHz you must move to AUC or LVC and drop the multi-gate quad packages — the parasitic capacitance of a four-gate die in SOIC-14 starts to dominate.

4. Output drive (I_OL/I_OH)

The HC family pushes 4–5.2 mA per pin at V_CC = 5V. AHC roughly doubles it to 8 mA, AUC delivers 9 mA at 1.8V, and LVC reaches 24–32 mA on the strongest variants. For driving a single CMOS input the HC numbers are fine; for driving a long PCB trace through a lossy connector, or for sinking an LED directly, prefer AHC or LVC.

5. Supply current and standby current (I_CC)

In a battery-powered IoT node, quiescent current is often the dominant logic-family selector. HC parts draw 2 µA static across the package; AUC drops this to 0.9 µA, and AUP variants reach 0.5 µA. If your sleep budget is 10 µA, an HC quad NOR alone consumes 20% of it; switching to a single-gate sub-1V NOR for ultra-low-power IoT nodes typically halves total logic-block leakage and pays back its small unit-price premium within the first month of field deployment.

6. Package and routing footprint

Quad NOR gates ship in SOIC-14, TSSOP-14, and SSOP-14. Single-gate variants in SOT-23-5, SC-70-5, and X2SON-6 are the right answer when the schematic only needs one or two NOR cells — populating four cells you do not use wastes board area and adds 12 input pins that must be tied off cleanly to avoid floating-input current spikes.

7. Operating temperature and reliability grade

Commercial-grade HC parts are rated −40 °C to +85 °C; the Q-suffix automotive variants extend to +125 °C with AEC-Q100 qualification. For industrial IoT (gateway boxes in unconditioned cabinets), specify Q-grade even if cost is 1.4× higher — field failures from un-spec'd thermal margins are the most expensive bug class in this category.

Recommended Products Comparison

The five parts below are stocked through FindMyChip's verified-distributor network, with quality_score ≥ 65 and on-shelf inventory at the time of publication.

Product	Family	V_CC Range	t_PD @ 5V	I_OL	Best For
SN74HC02DR	HC quad NOR	2–6 V	9 ns	5.2 mA	5V-only legacy designs, glue logic on a single rail
SN74HCT02N	HCT quad NOR	4.5–5.5 V	11 ns	4 mA	3.3V MCU driving 5V logic without an external level shifter
SN74AUC1G02DCKR	AUC single NOR	0.8–2.7 V	2.5 ns	9 mA	Battery-powered IoT, sub-3V rails
SN74AHC14N	AHC Schmitt inv	2–5.5 V	11 ns	8 mA	Slow / noisy sensor edges that need cleaning before logic
SN74LVC2G86DCUR	LVC dual XOR	1.65–5.5 V	4 ns	32 mA	Wide-rail XOR + level shifting in one part

When you have a BOM in hand, submit an instant quote or browse equivalents in our logic IC search.

Selection Decision Flowchart

Use this top-down decision path when picking between the five parts above.

Is your design 5V-only with no 3.3V/1.8V signals on the gate inputs?
- Yes → specify the SN74HC02 quad NOR. It is the cheapest, most second-sourced part in the lineup and remains the default for 5V glue logic.
- No → continue.
Are inputs driven by 3.3V GPIO into a 5V V_CC?
- Yes → specify its TTL-compatible HCT02 sibling. One part, no external level shifter, V_IH = 2.0V tolerates 3.3V GPIO down to 2.4V loaded.
- No → continue.
Is V_CC below 2.7 V (Li-coin, single-cell, or harvester rail)?
- Yes → specify a single-gate sub-1V NOR for ultra-low-power IoT nodes. Drops static I_CC below 1 µA per cell.
- No → continue.
Are you cleaning a slow or noisy edge (push-button, infrared receiver, capacitive sensor)?
- Yes → put a Schmitt-trigger inverter for noisy sensor lines ahead of the NOR. The hysteresis band typically spans 0.4–1.0V, which is enough to reject most ambient noise.
- No → continue.
Do you need XOR or generalized-gate behavior on a wide 1.65–5.5 V rail?
- Yes → specify a 1.65–5.5V XOR companion gate. Two cells per package keep the BOM tight and the LVC family stays in spec across all common IoT rails.

Using a NOR gate as a NOT gate (universal-gate trick)

Tie the two inputs of a NOR cell together and the output becomes the inversion of the input — a NOR has been turned into a NOT gate. Propagation delay does not change; the input capacitance roughly doubles because both pins now load the driver. Engineers who ask "how to use 74hc02 as a not gate or inverter" typically arrive here because they have already populated quad NORs and want to save a second IC for a single inverter — and the trick is correct so long as the doubled C_IN (typically 7 pF instead of 3 pF) is within the driving stage's slew budget. For IoT designs where two NOR cells are already in use as a set/reset latch, the remaining two cells in an SN74HC02 can absorb up to two NOT-gate equivalents at zero extra BOM cost.

Level shifting between 5V 74HC02 and 3.3V ESP32

If the gate's V_CC is fixed at 5V — for example because it drives a 5V relay coil or a 5V LED matrix — the input still has to read a 3.3V GPIO. There are three valid fixes, in order of preference:

Swap the gate for HCT. HCT inputs read TTL thresholds (V_IH = 2.0V), so an ESP32 GPIO at 3.3V is well above margin. This is the approach the spec sheet recommends and what the HCT family was originally designed for.
Add a discrete level shifter (BSS138 + pull-ups). Cheap and mechanically simple, but it adds 4 components per channel and 5 ns of asymmetric delay between rising and falling edges.
Move the entire gate to a 3.3V rail. Only valid if the downstream load also accepts 3.3V — common for chip-to-chip wiring, rare for relay or LED loads.

For a typical ESP32 + 5V load mix, route the GPIO to an HCT NOR and let one part do both the level shifting and the logic. The same logic applies to RP2040, ESP8266, STM32, or nRF52 GPIO sources — anywhere the silicon swings 3.0–3.3V and the downstream domain insists on 5V.

FAQ

Is SN74HC02 directly compatible with a 3.3V MCU output?

No, not when the gate's V_CC is 5V. HC-family inputs require V_IH ≥ 0.7 × V_CC = 3.5V at 5V supply, while a 3.3V GPIO swings to ~3.0–3.2V under load. The result is a logic-1 that lands inside the gate's undefined region. Switch to the HCT variant, or run the HC gate from the 3.3V rail if the downstream load tolerates it.

What is the difference between SN74HC02 and SN74HCT02?

Both parts implement the same quad 2-input NOR function and share the same pinout. The HC version uses CMOS input thresholds (V_IH = 0.7 × V_CC) and operates from 2–6V. The HCT version uses TTL input thresholds (V_IH = 2V minimum on a 5V rail), which lets it accept a 3.3V CMOS or 5V TTL drive into a 5V supply without an external level translator.

Can I use a 74HC02 as a NOT gate or inverter?

Yes. Tie the two inputs of one NOR cell together: when the input is high the NOR output is low, and when the input is low the NOR output is high — a clean inverter. The doubled input capacitance (typically 6–7 pF instead of 3 pF) is the only side effect. This is a common trick for absorbing extra inverter footprints into an already-populated SN74HC02 quad.

What logic family should I pick for a 1.8V IoT node?

Choose the AUC or AUP family. AUC parts run at 0.8–2.7V with sub-1 µA static current and 2.5 ns propagation delay; AUP is the lowest-power variant, optimized for sleep-heavy battery designs. Avoid HC and HCT below 2V — their AC parameters are not guaranteed in that range and propagation delay roughly triples.

How do I find a second source for SN74HC02DR in the China supply chain?

Pin-compatible second sources include 74HC02D from Nexperia, MC74HC02ADR2G from onsemi, and HD74HC02FPEL from Renesas/Hitachi heritage. All three are stocked through FindMyChip's verified-distributor network with anti-counterfeit verification on every reel. Submit the MPN list through the quote endpoint to receive availability and pricing across all distributors in one response.

Conclusion and next steps

The selection rules above collapse to four numbers worth memorizing: HC for 5V-only, HCT for 5V-supply-with-3.3V-drive, AUC for sub-3V rails, and LVC when you need a wide-rail or XOR variant in the same family. The five parts in the comparison table cover roughly 90% of NOR-gate slots in a typical IoT design.

When you are ready to populate the BOM, search the logic-IC catalog for live inventory or submit an instant RFQ for a multi-part quote across our 200+ verified-distributor network. We respond within 24 hours, and every reel ships with anti-counterfeit verification.