How to Choose Samsung CL05A106MP5NUNC 10uF 10V X5R 0402 MLCC: Selection Guide for Compact Decoupling

Bottom Line: When selecting the Samsung CL05A106MP5NUNC (10 µF, 10 V, X5R, 0402) for compact decoupling, three factors dominate the decision: DC bias derating (X5R loses roughly 50–60 % capacitance at its rated voltage, so a 10 V-rated part should see no more than 5–6 V in practice), package-vs-capacitance tradeoff (0402 gives maximum board density but demands careful PCB padstack design to avoid mechanical cracking), and dielectric choice (X5R delivers stable capacitance from −55 °C to +85 °C, making it the preferred alternative to X7R in space-constrained power rails). Verify your actual derating curve from the Samsung datasheet before committing to a design, and cross-check stock across 200+ verified distributors on FindMyChip /search.

Why the CL05A106MP5NUNC Matters for Compact Decoupling

The CL05A106MP5NUNC is Samsung Electro-Mechanics' 10 µF, 10 V, X5R MLCC in a 0402 (1005 metric) package. It represents the density frontier for bulk decoupling capacitors: packing 10 µF into a 1.0 mm × 0.5 mm footprint was impossible just a decade ago. Today it is the standard choice for DDR4/LPDDR4 power-supply decoupling, SoC VCC bypass on mobile boards, and any design where every square millimeter of PCB area is budgeted. Understanding its selection parameters helps you avoid costly respins.

Key Selection Parameter 1: DC Bias Derating (Capacitance vs. Voltage)

DC bias derating is the most frequently overlooked parameter for X5R MLCCs. When a DC voltage is applied, the ceramic lattice distorts and the effective capacitance drops sharply. For the CL05A106MP5NUNC at its rated 10 V, Samsung's derating curve shows effective capacitance falling to approximately 4–5 µF — a 50–60 % loss. At 5 V the derating is milder, retaining roughly 7–8 µF.

The practical rule: derate the working voltage to ≤ 50 % of the rated voltage to preserve most of the nominal capacitance. If your rail sits at 3.3 V, a 10 V-rated X5R 0402 gives you close to 9 µF of effective capacitance — a comfortable margin. If your rail is 5 V, consider whether a lower-capacitance but higher-voltage alternative maintains your required minimum at that node.

Comparison: the CL05A105KA5NQNC (1 µF, 25 V, X5R 0402) retains nearly 100 % capacitance on a 3.3 V rail because 3.3 V is only 13 % of its 25 V rating. For rails above 6 V, a higher-voltage-rated part may deliver more real-world capacitance than the CL05A106MP5NUNC even at smaller nominal values.

Key Selection Parameter 2: Temperature Stability (Dielectric Class)

X5R is a Class II dielectric rated for −55 °C to +85 °C with ±15 % capacitance variation over that range (EIA RS-198). It is the standard choice for most consumer, industrial, and telecom applications that do not exceed 85 °C. Above 85 °C, X7R (−55 °C to +125 °C) must be used; the CL05B104KO5NNNC (100 nF, 16 V, X7R, 0402) is a drop-in footprint alternative with better thermal stability but only 100 nF capacitance.

For automotive designs requiring AEC-Q200 qualification, neither X5R nor X7R in standard commercial grades is sufficient. Samsung's AEC-Q200 MLCC lineup uses a dedicated qualifier suffix. The CL05A106MP5NUNC carries no AEC-Q200 marking and should not be used in applications requiring that qualification without explicit OEM approval.

Temperature rise due to ESR-generated self-heating is also relevant. X5R MLCCs at 0402 exhibit ESR of approximately 5–20 mΩ at 1 MHz. At typical bypass capacitor ripple currents (50–500 mA), self-heating is negligible, but high-frequency DC-DC applications with large ripple current should verify the ripple current rating from the datasheet.

Key Selection Parameter 3: Package and Mechanical Considerations

The 0402 package (EIA 0402 / IEC 1005) measures 1.0 mm × 0.5 mm × 0.5 mm. Its small size reduces parasitic inductance — series inductance (ESL) is typically 0.5–0.8 nH for 0402 MLCCs versus 0.9–1.2 nH for 0603 — which translates directly to better high-frequency bypass performance above 10 MHz. For a 10 µF bulk bypass capacitor, the self-resonant frequency (SRF) lies roughly in the 2–5 MHz band; at frequencies above SRF the capacitor becomes inductive, so pairing with a 0.1 µF 0402 (e.g., cl05a104ka5nnnc) extends effective bypass bandwidth.

Mechanical robustness is the main risk. MLCC 0402 components are brittle ceramics susceptible to flex cracking if: (a) PCB assembly uses excessive solder paste, (b) the board undergoes mechanical bending during depaneling, or (c) conformal coating stress is applied. IPC-A-610 recommends placing small MLCCs away from board-edge regions susceptible to bending, with a minimum 2 mm clearance from V-score lines. Samsung's design guideline for CL05A series recommends a land pattern of 0.5 mm × 0.5 mm pads with 0.5 mm gap (verified in the Samsung MLCC Application Manual, 2022 edition).

Tombstoning (one end lifted during reflow) is more likely with asymmetric thermal mass or misaligned pad geometry. Follow IPC-7351 landpattern recommendations and ensure symmetric pad exposure on both terminations.

Key Selection Parameter 4: Capacitance Tolerance and Part Marking

The CL05A106MP5NUNC carries ±20 % tolerance (the "M" in the Samsung part number coding). This is typical for high-capacitance X5R MLCCs in 0402. Tighter ±10 % ("K" suffix) parts exist for 1 µF and below but are generally unavailable for 10 µF 0402 due to manufacturing process constraints. For decoupling applications, ±20 % tolerance is fully acceptable because decoupling capacitor values are not precision-critical; the important parameter is that effective capacitance at operating voltage exceeds the minimum required value.

The part number breakdown for Samsung CL series: CL (series) 05 (0402 EIA size) A (X5R dielectric) 106 (10 µF nominal, where 10 × 10^6 pF = 10 µF) M (±20 %) P (10 V rated) 5 (0.5 mm thickness) N (standard grade) U (paper taping, 4 mm reel) N (product status) C (SAM package class). Understanding this lets you decode alternative Samsung parts quickly.

Key Selection Parameter 5: Voltage Rating Margin and Reliability

IEC 60384-21/-22 and JEDEC standards recommend a 2:1 voltage derating for Class II ceramic capacitors in reliability-critical applications. For the CL05A106MP5NUNC rated at 10 V, this means a maximum continuous working voltage of 5 V. At 5 V, Samsung's qualification data shows MTTF > 10^8 hours (per Arrhenius acceleration model, 85 °C, 2× rated voltage stress conditions). Exceeding the rated voltage even briefly risks dielectric breakdown and catastrophic short-circuit failure.

For rails between 5 V and 12 V, consider the CL21A106KOQNNNE (10 µF, 16 V, X5R, 0805) which provides a better voltage margin at the cost of a larger 0805 footprint. If space is the constraint and the rail exceeds 6 V, upgrading to a 16 V or 25 V rated 0402 MLCC (at potentially lower capacitance) may be preferable.

Key Selection Parameter 6: Availability and Sourcing Considerations

The CL05A106MP5NUNC is a high-volume commodity MLCC. Normal lead times through authorized distributors are 4–12 weeks; spot market availability from Shenzhen distribution channels can reduce this to 1–3 days for quantities under 100K pieces. Price benchmarks (2024 spot market, >10K pcs): approximately USD 0.006–0.012 per piece through authorized distribution, USD 0.003–0.008 through independent distributors.

Counterfeit risk is low for commodity MLCCs compared to ICs, but remarked components (lower-specification parts relabeled as 10 µF) do appear in the spot market. FindMyChip's 5-point authentication process verifies lot traceability, package marking, and electrical characteristics. Use FindMyChip /quote to request verified pricing from 200+ pre-screened distributors simultaneously.

Recommended Products Comparison Table

Product	Capacitance	Voltage	Dielectric	Package	Tolerance	Best For
cl05a106mp5nunc	10 µF	10 V	X5R	0402	±20 %	3.3 V rail primary decoupling, dense boards
CL05A105KA5NQNC	1 µF	25 V	X5R	0402	±10 %	5–12 V rails, output filter, tighter tolerance
cl05a104ka5nnnc	100 nF	25 V	X5R	0402	±10 %	High-frequency bypass pair for 10 µF bulk cap
CL05B104KO5NNNC	100 nF	16 V	X7R	0402	±10 %	High-temp bypass (up to 125 °C), same footprint
CL21A106KOQNNNE	10 µF	16 V	X5R	0805	±10 %	5–12 V rails needing 10 µF, space available

Selection Decision Flowchart

Use this decision tree when selecting a compact decoupling MLCC:

1. What is your operating voltage?

   • ≤ 5 V → CL05A106MP5NUNC is ideal (effective ~7–9 µF at 3.3 V–5 V, 0402).
   • 5–12 V → Effective capacitance at 10 V is only 4–5 µF; consider CL21A106KOQNNNE (10 µF 16 V 0805) or accept reduced effective capacitance.

   • 12 V → The CL05A106MP5NUNC is outside rated voltage. Move to CL32B226KAJNNNE (22 µF 25 V 1210) or equivalent higher-voltage parts.

2. What is your operating temperature range?

   • −55 °C to +85 °C → X5R (CL05A series) is appropriate.
   • +85 °C to +125 °C → Switch to X7R (CL05B series), e.g. CL05B104KO5NNNC.
   • AEC-Q200 required → Use Samsung's automotive-qualified MLCC family (check suffix).

3. Is 0402 footprint mandatory?

   • Yes → CL05A106MP5NUNC is the highest capacitance available at 10 V in 0402.
   • No → CL21A106KOQNNNE (0805) offers ±10 % tolerance and 16 V rating, with more capacitance margin.

4. Do you need high-frequency bypass above 10 MHz?

   • Yes → Place a 100 nF 0402 (cl05a104ka5nnnc) in parallel to extend the flat impedance region beyond self-resonance.
   • No → A single CL05A106MP5NUNC per supply pin is sufficient for most MCU/SoC decoupling.

Frequently Asked Questions

What is the effective capacitance of the Samsung CL05A106MP5NUNC at 3.3 V? At 3.3 V DC bias, the CL05A106MP5NUNC retains approximately 85–90 % of its nominal 10 µF capacitance, giving roughly 8.5–9 µF effective capacitance. This is because 3.3 V is only 33 % of the 10 V rating, which lies in the low-derating region of the X5R curve. This makes it an excellent choice for 3.3 V MCU and SoC decoupling where 10 µF effective capacitance per supply pin is the design target.

Can the CL05A106MP5NUNC be used on a 5 V power rail? Yes, but with reduced effective capacitance. At 5 V (50 % of rated voltage), the effective capacitance drops to approximately 7–8 µF due to DC bias derating. This is still within most decoupling budgets for 5 V logic. However, for critical 5 V rails where the full 10 µF is required, consider using two CL05A106MP5NUNC capacitors in parallel, or upgrading to the CL21A106KOQNNNE (10 µF, 16 V, 0805) which retains close to full capacitance at 5 V.

What is the difference between X5R and X7R for MLCC decoupling? X5R (−55 °C to +85 °C, ±15 %) and X7R (−55 °C to +125 °C, ±15 %) are both Class II EIA dielectric codes. X7R handles higher temperatures but generally yields lower capacitance per unit volume than X5R at the same voltage and package size. For most consumer and industrial designs operating below 85 °C, X5R provides higher capacitance density — the CL05A106MP5NUNC achieves 10 µF in 0402 as a result. For automotive or industrial applications above 85 °C, the CL05B104KO5NNNC (X7R, 0402) is the thermally robust alternative, though only 100 nF at the same package size.

How do I avoid flex cracking in 0402 MLCCs? Flex cracking occurs when the PCB bends after assembly, stressing the brittle ceramic. Mitigation steps: (1) place 0402 MLCCs at least 2 mm from PCB edge and V-score lines; (2) use symmetric solder pad geometry per IPC-7351; (3) avoid excessive solder paste volume; (4) specify a controlled-flex PCB where board-edge depaneling applies stress. Samsung's CL05A series application note recommends reflow peak temperature ≤ 260 °C for 10 seconds and cooling rate ≤ 4 °C/second to minimize thermal shock cracking.

Where can I find verified stock for the CL05A106MP5NUNC? The CL05A106MP5NUNC is a high-volume commodity part stocked by major distributors globally. To compare pricing and availability across 200+ verified distributors simultaneously, use FindMyChip /search or submit a sourcing request via /quote. FindMyChip's 5-point authentication process screens for counterfeit and remarked components, ensuring lot traceability for every order.

Conclusion and Recommended Next Steps

The Samsung CL05A106MP5NUNC is the go-to 10 µF 0402 MLCC for 3.3 V power-rail decoupling on space-constrained PCBs. Its X5R dielectric delivers ≥ 8.5 µF effective capacitance at 3.3 V — sufficient for DDR, SoC, and MCU supply decoupling in the most compact form factor available. The primary design risks are DC bias derating on rails above 5 V and mechanical flex cracking; both are manageable with the guidelines above.

For a complete decoupling strategy: pair the cl05a106mp5nunc (10 µF bulk) with a cl05a104ka5nnnc (100 nF HF bypass) at each supply pin, and verify effective capacitance at your operating voltage using Samsung's MLCC DC bias derating tool. When sourcing in volume, use FindMyChip /search to get competitive quotes from verified distributors and protect against counterfeit risk.