LM66100QDCKRQ1 Design Guide: Ideal Diode and Reverse Polarity Protection for Automotive Power Rails

Bottom Line: The LM66100QDCKRQ1 is an AEC-Q100 automotive-grade ideal diode controller that replaces a standard Schottky with a near-zero forward-voltage drop path: it drives an external PMOS to near-full enhancement, dissipating less than 1 mW at 1 A instead of the 600 mW a 0.6 V Schottky would. Three design decisions dominate every deployment — PMOS sizing for RDS(on) and SOA, threshold tuning via VREF pin, and reverse-polarity protection integration — and getting all three right is the difference between a robust automotive power rail and a field failure.

What Is the LM66100QDCKRQ1?

The LM66100QDCKRQ1 is a ±6 V, low-IQ ideal-diode and polarity-protection controller from Texas Instruments, qualified to AEC-Q100 Grade 1 (−40 °C to +125 °C). It is packaged in a 6-pin SC-70, occupies only 2 mm × 2.1 mm of board area, and draws a quiescent current of just 16 µA in forward conduction mode. Unlike a conventional Schottky diode, the device uses a comparator-based gate drive to fully enhance an external PMOS transistor whenever VAnode > VCathode, delivering a forward voltage that is limited only by the MOSFET's RDS(on) — typically 3–8 mΩ for a modern 30 V PMOS.

The device is widely used in automotive infotainment, body-electronics, and ADAS power rails where CISPR 25 radiated-emission limits and ISO 7637 transient-immunity requirements must be met simultaneously. The companion device LM66100DCKR covers the same ±6 V range in a commercial temperature grade for industrial or consumer applications.

Design Consideration 1 — PMOS Selection and RDS(on) Budget

Selecting the right PMOS transistor is the single largest factor in system efficiency, because the LM66100 is only as good as the FET it drives. The controller charges the gate to within ~100 mV of the source rail in steady state, so the effective RDS(on) is very close to the datasheet value at VGS = −5 V. For a 2 A load on a 12 V automotive rail, a PMOS with RDS(on) ≤ 50 mΩ keeps conduction loss below 200 mW — well within the thermal budget of a small SOT-223 package at 125 °C ambient. The device handles input voltages from −0.3 V to +6 V, so external clamp circuitry is needed for 12 V automotive rails; TI recommends a resistive voltage divider on the GATE/IN pins combined with a Zener clamp (see SLVA801 for detailed resistor selection equations).

Key PMOS parameters to verify in your BOM:

BVDSS ≥ 30 V to survive ISO 7637-2 pulse 1 and pulse 2b transients.
QGD ≤ 5 nC to limit switching loss during dynamic diode-OR transitions.
SOA curve at the expected worst-case inrush current (typically 5–10× steady-state for cold-crank events).

Design Consideration 2 — Threshold Voltage and the VREF Pin

The LM66100's forward-voltage threshold is programmable via an external resistor divider on the VREF pin, allowing the designer to trade off reverse-recovery speed against false-turn-off immunity. The default open-circuit threshold is +8 mV (anode relative to cathode). Raising it to 20–30 mV via a 1 MΩ pull-up to VAnode increases noise immunity on noisy automotive bus segments; lowering it toward 4 mV accelerates turn-off when load-dump transients reverse the supply. The formula from the datasheet:

VTHRESHOLD = VREF × (R1 + R2) / R2

where R1 is tied between VREF and VANODE, and R2 between VREF and GND. A typical automotive target is VTHRESHOLD = 15 mV with R1 = 150 kΩ and R2 = 1 MΩ. Do not use resistors below 100 kΩ: the VREF input impedance is ~10 MΩ, so large resistors do not load the node, but small ones waste quiescent current.

Design Consideration 3 — Reverse Polarity Protection (RPP) Integration

Integrating RPP with ideal-diode control in a single PMOS eliminates the second series device that a discrete Schottky + RPP architecture would require, reducing BOM count by 2–3 components. When the input rail goes negative (battery reverse connection), the LM66100 pulls the MOSFET gate high within ~1 µs, turning the FET off and blocking reverse current. The PMOS body diode is momentarily forward-biased during this 1 µs window, but the peak reverse-current pulse energy (typically < 0.5 mJ at 12 V, 10 ms pulse per ISO 16750-2 test 4.6.1) is well within the body-diode rating of any 30 V PMOS.

For systems that must also block reverse currents from the output side (ORing two supply rails), use two LM66100-driven PMOS devices back-to-back with sources tied together. The controller correctly handles both polarity conditions independently on each device. Verify that the diodes-OR rail does not exceed +6 V; for 12 V and 24 V buses use the LM74202QPWPRQ1 (40 V, 2.2 A integrated FET) or the LM74502QDDFRQ1 (65 V, external NMOS RPP controller).

Design Consideration 4 — Thermal Management in Automotive Environments

Junction temperature must stay below 125 °C under the worst-case combination of maximum load current, maximum ambient temperature, and minimum PCB copper area. The SC-70 package has a θJA of ~280 °C/W with the minimum JEDEC single-layer PCB layout and ~200 °C/W with 1 oz copper pour. Since the LM66100 itself dissipates only the gate-drive and quiescent power (< 1 mW total), thermal design is entirely dominated by the external PMOS. Size the FET footprint copper pour to hold TJ ≤ 125 °C at 125 °C ambient using:

TJ = TAMB + (ILOAD² × RDS(on) × θJA_FET)

For a 30 V PMOS in SOT-223 with RDS(on) = 25 mΩ at 125 °C and θJA = 40 °C/W, the maximum continuous load current at 125 °C ambient is approximately 3.5 A — a common automotive BCM power-path design point.

Design Consideration 5 — Layout Guidelines for EMC Compliance

Proper PCB layout is mandatory for passing CISPR 25 Class 5 limits; poor layout can inject switching noise onto the vehicle LIN or CAN bus even at the LM66100's low 16 µA IQ. Follow these practices:

Place a 100 nF, X7R, 0402 bypass capacitor directly on the VAnode pin to GND, with trace length < 3 mm.
Route the GATE trace with a maximum length of 15 mm and shield it from high-dV/dt nodes with a ground guard trace.
Keep the VREF resistor network within 5 mm of the IC to minimize capacitive pickup.
Add a 10 Ω series gate resistor to limit dI/dt during turn-on (reduces conducted emissions on the input rail).
Use a single-point ground star topology — merge the signal GND and power GND at one via cluster near the IC.

Parameter	Value
Input voltage	5 V – 12 V
Max load current	1 A
Conduction loss at 1 A	~10 mW (RDS(on) = 10 mΩ PMOS)
Reverse response time	< 1 µs
Package area	< 10 mm²

Parameter	Value
Input voltage	8 V – 16 V
Max load current	4 A
Conduction loss at 4 A	~240 mW
Required PMOS package	DPAK / D2PAK
Applicable standard	AEC-Q100 Grade 1, ISO 7637-2

Parameter	LM66100QDCKRQ1	LM74610QDGKRQ1	LM74202QPWPRQ1
Input range	±6 V	±100 V	4.5 V – 40 V
Integrated FET	No	No	Yes
IQ	16 µA	~1 µA	40 µA
AEC-Q100	Yes	Yes	Yes

Common Pitfalls and Troubleshooting

Pitfall 1 — Exceeding ±6 V Common-Mode Range Without a Clamp

Mistake: Directly connecting the LM66100 to a 12 V automotive rail without a resistive divider or Zener clamp on the IN/GATE pins. Consequence: The controller's absolute maximum input voltage is ±6 V. Exceeding it permanently damages the gate-drive comparator — a failure mode that may not surface until a load-dump event. Fix: Use a series resistor (10 kΩ) and Zener clamp (5.1 V) on the IN pin as shown in Figure 5 of the LM66100 datasheet (SNVSA15).

Pitfall 2 — Body Diode Conduction After Power Loss

Mistake: Assuming the PMOS body diode blocks reverse current when VIN drops to 0 V faster than the controller can respond. Consequence: During a fast load-dump clamp, the body diode may conduct for 1–5 µs, injecting current back into the supply. Fix: Add a 100 µs RC delay on the GATE drive (1 MΩ + 100 nF) to hold the FET on during brief input glitches, then use the VREF threshold to ensure turn-off only on genuine reverse conditions.

Pitfall 3 — Floating VREF Pin Causes Threshold Drift

Mistake: Leaving the VREF pin unconnected and relying on the internal default. Consequence: PCB leakage currents or ESD charges can shift the threshold unpredictably at high temperature. Fix: Always tie VREF to a defined voltage via a resistor divider, even if you want the default 8 mV threshold. Use R1 = 0 Ω (short) and R2 = 1 MΩ to GND to anchor the node while keeping the nominal threshold.

Pitfall 4 — Gate Resistor Too Large Slows Turn-Off

Mistake: Using a 1 kΩ gate resistor to suppress ringing, which extends turn-off to > 10 µs. Consequence: Extended reverse-current conduction during hot-swap or ORing events heats the PMOS beyond its SOA. Fix: Keep the gate resistor ≤ 47 Ω. For larger FETs (DPAK and above), use a gate resistor of 10 Ω combined with a 1 nF gate-to-gate bypass to ground to damp oscillation without lengthening the turn-off transient.

Pitfall 5 — Ignoring PMOS VGS(th) at High Temperature

Mistake: Selecting a PMOS with VGS(th) = −2 V at 25 °C without checking the high-temperature datasheet curve. Consequence: At 125 °C, VGS(th) often drops to −0.8 V, meaning a logic-level PMOS may enter linear region earlier and increase RDS(on) by 3–5×. Fix: Choose automotive-grade PMOS devices with VGS(th) characterized across temperature, and verify RDS(on) at VGS = −5 V (the LM66100's typical gate drive) at 125 °C.

FAQ

Q: Can the LM66100QDCKRQ1 be used for battery ORing with two 12 V lithium packs? A: Not directly — the ±6 V common-mode input range limits direct use on 12 V rails. Use an external resistive divider and Zener clamp to bring the IN-pin voltage within ±6 V. For native 12 V ORing, consider the LM74610QDGKRQ1 (100 V) or add a supervised gate-drive circuit per TI application report SLVA801.

Q: What is the reverse-polarity response time? A: Typically under 1 µs from the moment VANODE goes 8 mV below VCATHODE to the GATE rising to VCC. This is fast enough to limit body-diode conduction energy to < 0.5 mJ on a 12 V / 10 ms ISO 16750-2 reverse-polarity pulse — well within the SOA of any 30 V PMOS.

Q: Is the LM66100QDCKRQ1 pin-compatible with the non-Q1 version? A: Yes. The LM66100QDCKRQ1 and LM66100DCKR share identical pinouts in the SC-70-6 package. The Q1 suffix indicates AEC-Q100 Grade 1 qualification, PPAP documentation support, and a controlled change notice process — functionally the devices are equivalent.

Q: How does the LM66100 compare to a Schottky diode on bill-of-materials cost? A: A comparable 1 A / 30 V Schottky (e.g., MBRS130LT3G) costs roughly $0.05 in volume. The LM66100QDCKRQ1 plus an external PMOS is $0.35–$0.50 in 1k volumes. The ~$0.30 premium is recovered in 3–6 months of field operation through energy savings alone at 1 A continuous load; at 4 A the payback is under one month.

Q: What package options are available? A: The SC-70-6 (DCK) package is the only offering for the LM66100 family. The LM66100DCKT is a tape-and-reel variant of the non-automotive grade. For applications needing a larger package footprint for thermal reasons, TI's LM74202QPWPRQ1 (HTSSOP-16) integrates the FET and provides 40 V input capability.

Conclusion

The LM66100QDCKRQ1 is the right choice for any automotive power-path design that needs both ideal-diode efficiency and reverse-polarity protection within a 6 V common-mode window. Key takeaways:

Efficiency: Replace a 600 mW Schottky loss with < 30 mW using a 7.5 mΩ PMOS and LM66100 gate drive.
Protection: < 1 µs reverse turn-off eliminates the need for a dedicated RPP device in most body-electronics designs.
Scalability: For higher voltages, the LM74610QDGKRQ1 and LM74202QPWPRQ1 extend the same architecture to 100 V and 40 V respectively.

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