ICL7660ACPAZ Negative Voltage Charge Pump Design Guide

Bottom Line: Use the ICL7660ACPAZ when a board needs a low-current negative rail from a positive 1.5 V to 10 V supply and isolation is not required. Size the flying and output capacitors from load current, oscillator frequency, and allowed ripple rather than copying a nominal 10 uF example blindly. Keep the charge-pump loop compact, verify the worst-case output as (V_{OUT} \approx -V_{IN} + I_{OUT}R_{OUT}), and reserve margin for capacitor ESR, switch resistance, temperature, and startup load. The device is a practical fit for op-amp bias, sensor conditioning, and interface circuits, but it is not a substitute for an inductor-based converter when current, regulation, or EMI requirements are demanding.

The ICL7660ACPAZ is a CMOS switched-capacitor voltage converter commonly used to create a negative supply from an existing positive rail. Unlike an inductor converter, it transfers charge through a flying capacitor, which keeps the bill of materials small and avoids a magnetic component. That simplicity comes with clear limits: output resistance rises at light switching frequency, available current is modest, and output ripple depends directly on capacitance, ESR, and load.

This application note focuses on an inverting design, where the nominal output is approximately the negative of the input. It explains the calculations, component choices, layout decisions, and validation tests needed to turn a schematic-level charge pump into a reliable production circuit.

1. Confirm That a Charge Pump Fits the Load

A switched-capacitor inverter is the right architecture only when the negative rail requires modest current and can tolerate load-dependent voltage drop. Start from the maximum continuous and transient load, not from the no-load output voltage. Typical loads include op-amp negative rails, small analog switches, LCD bias nodes, sensor interfaces, and reference or guard circuits.

The first-order loaded output is:

[ V_{OUT} \approx -V_{IN} + I_{OUT}R_{OUT} ]

Here, (R_{OUT}) is the charge pump's effective output resistance, incorporating internal switch resistance, flying-capacitor impedance, capacitor ESR, and layout resistance. Because (V_{OUT}) is negative, the positive (I_{OUT}R_{OUT}) term makes its magnitude smaller. For example, a 5 V input, 10 mA load, and 35 ohm effective output resistance would yield roughly -4.65 V before output ripple is included.

Do not equate a headline efficiency percentage with tight regulation. Charge-transfer efficiency may be high at favorable operating points while the negative rail still changes by hundreds of millivolts as load rises. If the application needs more than a few tens of milliamps, a tightly regulated rail, or large transient current, compare an inverting buck-boost or transformer-based converter before committing to the ICL7660A architecture.

Use at least four load cases in the design specification: no load, typical load, maximum continuous load, and maximum transient load. Record the allowed average voltage, ripple peak-to-peak, recovery time, and startup behavior for each case. This converts an ambiguous requirement such as “about -5 V” into measurable acceptance criteria.

2. Respect Input Voltage and Pin Configuration Limits

The input rail, device variant, and low-voltage pin configuration must be checked together against the exact manufacturer datasheet. ICL7660-family parts span different voltage limits, oscillator options, packages, and temperature grades, so a familiar family name does not make every suffix interchangeable. The ICL7660A family is generally used across a 1.5 V to 10 V supply range, but the production schematic and BOM should cite the limits for the exact ordering code.

For supplies above the low-voltage threshold specified in the datasheet, configure the LV function exactly as recommended; for low input operation, the alternate connection reduces internal losses. An incorrect LV connection can increase output resistance or violate a pin limit even when the input voltage itself appears valid. Treat the OSC, BOOST, and LV pins as functional analog nodes rather than unused logic pins, and never leave a pin in a state the datasheet does not define.

Add local input bypassing at the device because the input current is pulsed. A 100 nF ceramic capacitor in parallel with a larger local reservoir is a common starting point, but the reservoir value should be verified against source impedance and ripple current. If the input comes through a long cable, ferrite bead, current-limited LDO, or high-resistance trace, simulate or measure the droop at the charge-transfer edges.

Absolute maximum ratings are not operating targets. Apply design margin to supply tolerance, hot-plug overshoot, reverse connection, and any positive or negative transient coupled from the output. For a 10 V-rated operating range, a nominal 10 V rail with positive tolerance may already leave insufficient margin unless the source is tightly controlled.

3. Size the Flying Capacitor From Charge Transfer

The flying capacitor sets a fundamental part of output resistance, so it must be selected from current and switching frequency. A useful first approximation for the capacitor-related resistance is:

[ R_{FLY} \approx \frac{1}{f_{OSC}C_{FLY}} ]

This term is only part of total (R_{OUT}), but it shows the direction clearly. At 10 kHz, 10 uF contributes about 10 ohms before switch resistance, ESR, and topology factors are considered; reducing it to 1 uF increases that term by approximately ten times. The final value should follow the device datasheet's recommended range and be validated at the lowest effective capacitance.

Capacitor label value is not effective capacitance. Class II ceramics can lose a large fraction of nominal capacitance under DC bias, while aluminum electrolytic ESR rises at low temperature. Tantalum and polymer parts may hold capacitance more consistently, but their surge, leakage, and derating rules must be respected.

Check these parameters for the flying capacitor:

1. Effective capacitance at the actual DC and AC voltage.
2. ESR across the full temperature and frequency range.
3. Ripple-current rating and self-heating.
4. Voltage rating with at least the project's required derating.
5. Leakage current, which matters most at light load.

The common mistake is to replace a through-hole electrolytic with a physically small ceramic of the same printed value without checking DC-bias curves. The prototype may work at room temperature, then show excessive output sag when the effective capacitance falls under bias or component tolerance.

4. Size the Output Capacitor for Ripple and Recovery

The output capacitor must satisfy both steady-state ripple and transient recovery requirements. A practical ripple estimate is:

[ \Delta V_{OUT} \approx \frac{I_{OUT}}{f_{OSC}C_{OUT}} + I_{PULSE}ESR_{OUT} ]

The first term describes charge removed between refresh cycles; the second captures the instantaneous step across ESR. With 10 mA load, 10 kHz switching, and 10 uF effective capacitance, the ideal capacitive term alone is about 100 mV peak-to-peak. Real ripple will be higher because current is transferred in pulses and the capacitor and interconnects are nonideal.

If the target is 25 mV peak-to-peak at the same load and frequency, the simple capacitive calculation suggests at least 40 uF effective capacitance before ESR and tolerance are added. That may push the design toward a 47 uF or larger part, or toward a post-filter and lighter dynamic load. Increasing capacitance also increases startup charge and can stress a current-limited source, so verify startup rather than assuming more capacitance is always better.

A small RC or ferrite-capacitor post-filter can reduce high-frequency ripple for a noise-sensitive analog load. Its series element causes additional DC drop and can interact with the load's transient demand. Never add an LC network without checking damping; a lightly damped filter may ring when the pump switches or the load steps.

Measure ripple with a short ground spring or coaxial tip at the load. A long oscilloscope ground lead can display loop pickup that is not present on the rail, while excessive bandwidth can hide the difference between low-frequency pump ripple and fast switching spikes. Report both a bandwidth-limited result, such as 20 MHz, and a full-bandwidth capture when the system's noise requirement calls for it.

5. Control Switching Noise Through Layout

The highest-current charge-transfer loop must be physically small to prevent a simple charge pump from becoming a board-level noise source. Place the flying capacitor directly beside the associated pump pins and keep both traces short, wide, and on one layer where possible. Place the output capacitor close to the output and ground pins, and connect the input bypass capacitor through a low-inductance path.

Route the negative output away from high-impedance inputs, oscillators, ADC references, crystal networks, and RF matching structures. If the negative rail feeds an op amp, separate the pump's pulsed return current from the amplifier's signal ground until both reach a controlled star or plane connection. A continuous reference plane normally outperforms a fragmented ground path, provided the charge-transfer loop does not cross a sensitive region.

Do not place a test point stub or long via chain inside the flying-capacitor loop. Even when DC resistance is negligible, added inductance increases switching spikes. If a probe point is necessary, place it outside the critical loop and provide an adjacent ground pad for a low-loop-area connection.

The oscillator frequency and harmonics should be compared with the signal band. A 10 kHz-class pump can fall inside audio or precision sensor bandwidth, while its edges generate much higher harmonics. If the application cannot filter these components or tolerate beat frequencies, consider a higher-frequency family variant, synchronization-capable converter, or regulated inverting converter.

6. Plan Startup, Shutdown, and Fault Behavior

Startup and fault behavior must be tested with the real load because the charge pump has limited current available to charge the negative rail. At startup, the output capacitor begins discharged and appears as a large load. A downstream circuit that conducts heavily before its negative rail is established can delay startup further or hold the rail at an intermediate voltage.

Estimate an ideal minimum charge time from (t \approx C_{OUT}\Delta V/I_{AVAILABLE}), then expect the measured time to be longer because pump current falls as the output approaches its final voltage. For 47 uF charged across 5 V with 10 mA available, the idealized result is 23.5 ms. Source current limit, flying-capacitor value, internal resistance, and the active load can extend it substantially.

Check whether the downstream IC tolerates its positive rail arriving before the negative rail. Some analog inputs can conduct through protection structures when one supply is absent. Series resistance, input sequencing, an enable function elsewhere in the system, or a discharge path may be required to keep pin currents within rated limits.

Also test output short circuit, accidental positive voltage applied to the negative node, input brownout, and rapid power cycling. The device should not be assumed to provide programmable current limiting or precision thermal protection. If a fault can persist, add upstream current limitation or protection appropriate to the product's safety and reliability requirements.

Recommended Solutions

The best implementation depends on package, load current, noise budget, and production assembly rather than on conversion ratio alone. The following three solutions use searchable ICL7660-family candidates while preserving the same basic inverting topology.

Solution A: ICL7660ACPAZ for General Low-Current Negative Rails

Use the ICL7660ACPAZ with a flying capacitor and output capacitor selected from the calculations above. This ordering code is a practical starting point for through-hole prototyping and low-volume assemblies where easy handling matters. Begin with the datasheet reference circuit, then validate effective capacitance and loaded output at input, load, and temperature corners.

The main advantages are a two-capacitor conversion core, no inductor, and a direct -VIN nominal output. The disadvantages are finite output resistance, pump-frequency ripple, and limited current. This solution fits analog bias rails and interface circuits where the load is predictable and the downstream circuit tolerates some voltage variation.

Solution B: ICL7660ACBAZA for Surface-Mount Production

Use the ICL7660ACBAZA when a surface-mount package is preferable and the exact package, temperature grade, and electrical limits meet the design. The electrical design method remains the same, but a smaller package often enables a tighter flying-capacitor loop. It can therefore reduce parasitic inductance compared with a socketed prototype.

The advantage is production-friendly assembly and potentially better high-frequency layout. The tradeoff is reduced ease of rework and a different thermal and mechanical footprint. Do not substitute it on the BOM solely because the family prefix matches; confirm pinout, land pattern, grade, and lifecycle status.

Solution C: ICL7660SCBAZ When the S-Variant Features Are Needed

Consider the ICL7660SCBAZ when the system benefits from the S-family's variant-specific oscillator or voltage-range features. Treat it as a separate design choice, not an automatic drop-in upgrade. Recalculate capacitor impedance at the actual switching frequency and recheck EMI, because changing frequency affects both ripple and spectral content.

The potential benefit is lower capacitor-related output resistance or easier filtering when the selected operating mode uses a higher switching frequency. The costs may include higher switching loss, different pin usage, and a revised noise profile. This solution is best when a datasheet-level comparison shows that its features solve a measured limitation in the A-family design.

Design option	Primary reason to choose it	Main benefit	Main caution
ICL7660ACPAZ	General design or through-hole prototype	Simple implementation and easy handling	Validate loaded voltage and ripple
ICL7660ACBAZA	Surface-mount production	Compact layout around flying capacitor	Confirm package and grade details
ICL7660SCBAZ	S-variant feature set is required	Potential frequency or range advantage	Recalculate noise and capacitor behavior

Engineers can search FindMyChip's component database to compare current package and manufacturer records. For production quantities or hard-to-source suffixes, submit the BOM through the 24-hour RFQ channel; FindMyChip connects buyers with more than 200 verified distributors and applies a five-point authentication process.

Common Pitfalls and Troubleshooting

Most ICL7660A failures trace to underestimated output resistance, weak capacitor selection, or a large switching loop. The following checks isolate those causes quickly.

Pitfall 1: The Output Is Correct With No Load but Collapses in Circuit

The likely cause is load current multiplied by effective output resistance. Measure load current and sweep it with an electronic load while recording average output voltage. Increase effective flying capacitance within datasheet limits, reduce capacitor ESR and trace resistance, or move to a converter designed for the required current.

Pitfall 2: Ripple Is Much Higher Than the Calculation

The common causes are DC-bias capacitance loss, high ESR, excessive probe loop area, or unexpected pulsed load current. Verify the capacitor vendor's bias curve and repeat the measurement with a ground spring. If the waveform changes with probe technique, separate real rail ripple from magnetic pickup before changing the PCB.

Pitfall 3: The Analog Channel Shows a 10 kHz-Class Spur

The pump current is coupling through power, ground, or electric-field paths. Inspect the PCB current loop, separate sensitive routing, and add a deliberately designed post-filter if the DC drop is acceptable. Changing capacitor values without fixing the coupling path may reduce the fundamental but leave edge-related harmonics.

Pitfall 4: Startup Is Slow or Stops at an Intermediate Voltage

The output capacitor or downstream circuit is demanding more current than the pump can initially deliver. Disconnect the load to distinguish converter startup from load interaction, then reconnect loads in stages. Reduce startup capacitance, delay the load, limit its inrush, or select a converter with more startup current.

Pitfall 5: A Second-Source Suffix Does Not Behave the Same

Family-compatible devices can differ in maximum voltage, oscillator frequency, boost behavior, LV-pin recommendations, package, and temperature grade. Compare complete datasheets and ordering tables, not just the ICL7660 name. Requalify output voltage, ripple, startup, and EMI after any manufacturer or suffix change.

FAQ

How much current can an ICL7660ACPAZ negative rail deliver?

There is no single useful current answer without an allowed voltage-drop limit. Calculate or measure effective output resistance, then use (|V_{OUT}| \approx V_{IN} - I_{OUT}R_{OUT}) to find the current that still meets the rail specification. Include ripple, temperature, input tolerance, and transient load; if the design needs tens of milliamps with tight regulation, evaluate a regulated inverting converter.

What capacitor values should I use with the ICL7660ACPAZ?

Ten-microfarad flying and output capacitors are a common starting point for ICL7660-class reference circuits, but they are not universal production values. Select the flying capacitor from (1/(fC)) impedance and the output capacitor from allowed ripple, then check effective capacitance, ESR, leakage, voltage derating, ripple current, and temperature. Validate the exact values against the current device datasheet.

Can the ICL7660ACPAZ generate exactly -5 V from +5 V?

Not under load without post-regulation. The ideal no-load conversion approaches -VIN, but switch resistance, flying-capacitor impedance, ESR, and load current reduce the magnitude. If the circuit requires an accurate -5.00 V rail, allow headroom and add regulation, or use an inverting regulator whose feedback loop directly controls output voltage.

Is an ICL7660A suitable for low-noise analog circuits?

It can be suitable when load current is small, the charge-transfer loop is compact, and filtering keeps the pump frequency and harmonics outside the error budget. Measure noise at the load with proper probing and under realistic signal conditions. Precision audio, sensor, or data-converter systems may need a post-filter, a higher-frequency variant, or a different converter architecture.

Can I cascade two ICL7660 stages for a larger negative voltage?

Cascading is possible in some charge-pump topologies, but each stage adds output resistance, ripple, startup time, and device-stress constraints. Check every pin's voltage relative to its local rails and stay within the exact datasheet ratings. For meaningful load current or a tightly controlled higher-magnitude rail, a purpose-built inverting or isolated converter is usually easier to validate.

Conclusion

A reliable ICL7660ACPAZ inverter comes from budgeting voltage drop and ripple before selecting capacitors. Confirm that a charge pump matches the load, calculate flying- and output-capacitor requirements, keep the switching loop compact, and test startup and faults with the real downstream circuit. The resulting design can provide a compact negative bias rail with only a few external components.

For sourcing, compare the ICL7660CPAZ alongside the A-grade candidate and confirm the exact electrical and package requirements before substitution. FindMyChip's verified distributor network can help locate production quantities, compare traceability documentation, and respond to a component quote request within 24 hours.