CL32B226KAJNNNE 22µF 25V MLCC Application Note: Bulk Decoupling and Bypass Design

Bottom Line: The Samsung CL32B226KAJNNNE delivers 22 µF at 25 V in a 1210 package, but DC-bias derating cuts effective capacitance to roughly 8–12 µF at its rated voltage—plan your bulk-decoupling budgets around measured, not nominal, capacitance. Mount it within 2 mm of the regulator output pin on a 4-layer board with a low-inductance via pair to minimize ESL, and apply flex-termination pads or a soft-termination variant if the board experiences mechanical stress. Pair a 22 µF bulk cap with a 100 nF or 10 µF X7R bypass cap on the same rail for broadband transient suppression from DC to >10 MHz.

DC-Bias Capacitance Derating at 25 V Rails

DC-bias derating is the single most underestimated loss in ceramic bulk-decoupling design. X7R Class II MLCCs use barium titanate dielectrics whose permittivity drops sharply under applied electric field; the CL32B226KAJNNNE (22 µF, 25 V, X7R, 1210) typically retains only 40–55 % of its nominal capacitance when biased at its rated 25 V—a loss of 10–13 µF before frequency or temperature effects are even considered. JEDEC JEP117 and IEC 60384-22 both require characterizing derating over voltage, temperature, and frequency, yet most board-level budgets still use the 0 V nominal value.

To budget correctly, use the capacitor's C-V curve from the Samsung Electro-Mechanics datasheet or SPICE model. At 25 V, plan for an effective capacitance (C_eff) of 9–12 µF. For a 3.3 V rail derived from a 25 V bus through a linear or switching stage, the capacitor is biased at 3.3 V—derating to roughly 18–20 µF—so voltage domain matters. If your rail sits near 25 V (e.g., 24 V industrial bus), you must either use a higher-voltage part (e.g., 50 V rated) or stack multiple capacitors in parallel.

When three CL32B226KAJNNNE units are placed in parallel on a 24 V rail, nominal capacitance is 66 µF but effective capacitance is only ~30–36 µF at 24 V bias—still adequate for most 10 A switching supplies with <200 mV ripple targets, but the designer must verify against the C-V curve, not the data sheet header. Use an LCR meter with DC-bias capability (e.g., Keysight E4980A) or the MLCC DC-bias measurement technique from TI Application Report SLTA014.

Temperature adds a secondary derating: X7R is rated ±15 % ΔC over −55 °C to +125 °C per EIA-198, but at elevated temperature plus high bias the compound loss can reach 60–70 % of nominal. Always simulate the worst-case corner (high temperature + rated voltage) using the capacitor vendor's SPICE model.

1210 Board Flex and Mechanical Crack Mitigation

Mechanical cracking is the leading field-failure mode for 1210 and larger MLCC packages. The 1210 (3225M) case body is 3.2 mm × 2.5 mm × 1.25 mm nominal; the rigid ceramic body has zero ductility, so any PCB flexure exceeding roughly 2–3 mm deflection over a 90 mm span (IPC-9704 standard flex test) can initiate cracks near the termination ends. Cracks typically manifest as intermittent shorts or parametric drift rather than immediate open circuits, making them difficult to detect in functional test.

Mitigation at the layout level begins with routing: never place a 1210 MLCC within 1.5 mm of a panel-breakout scoring line, a mounting-hole edge, or a PCB press-fit connector footprint. JEDEC JESD22-B110 specifies board-flex test severity levels; target severity level B or better for consumer products and level A for industrial/automotive. If a 1210 cap must be near a flex zone, rotate it 90° so its termination axis is parallel to the bend axis, which reduces stress concentration.

Flex-termination (soft-termination) capacitors add a conductive-polymer layer between the ceramic body and the tin-plated external termination, absorbing mechanical strain. Samsung Electro-Mechanics' "KM" suffix series (e.g., CL32B226KAJNNNE-equivalent in flex-termination) provides this feature; the CL21B106KOQNNNE 0805 variant is also available in soft-termination form for less-critical rails. Expect a 10–15 % cost premium for the flex-termination SKU, which is almost always justified for boards that experience thermal cycling in automotive, outdoor, or industrial environments.

Solder profile also affects crack risk: a peak reflow temperature of 245–250 °C per IPC-7711/7721 with a ≤3 °C/s cooling ramp is the Samsung Electro-Mechanics guideline. Faster cooling increases thermal-shock stress on the termination joint. Avoid no-clean flux formulations that leave ionically active residues near the capacitor body if the board will operate in humid environments (IEC 60068-2-67 test Eh).

Bulk-Decoupling Placement Near Regulators

Placement determines effective decoupling more than capacitance value for frequencies above 1 MHz. The CL32B226KAJNNNE is optimally suited for bulk decoupling in the 100 kHz–5 MHz range; its self-resonant frequency (SRF) is typically 2–4 MHz for a 22 µF 1210 MLCC, above which inductive behavior dominates. For a DC/DC switching converter operating at 300 kHz–1 MHz (e.g., a TPS54531 at 500 kHz), place the 22 µF bulk cap within 2 mm of the output inductor's load-side pad and the IC's output-sense pin.

Use a pair of 0.3 mm vias connecting the capacitor pad directly to the power and ground planes; a single via adds 0.5–1 nH of inductance that significantly degrades high-frequency impedance. Four-layer stackup with a dedicated power plane adjacent to ground plane (e.g., Layer 2 = GND, Layer 3 = VCC) provides 50–80 pH/mm² interplane capacitance that supplements the discrete MLCC. Per TI Power Design Seminar SEM2200 (2020), the decoupling impedance target for a 3.3 V/10 A rail is typically <10 mΩ from DC to 10 MHz.

A complete bulk-decoupling network for a 25 V-input, 3.3 V/5 A switching regulator typically combines: one CL32B226KAJNNNE (22 µF, bulk energy storage and low-frequency filtering), one CL21A106KOQNNNE (10 µF 0805, mid-frequency bypass), and one CL21B104KBCNNNC (100 nF 0805, high-frequency bypass). This three-tier ladder covers DC–100 kHz, 100 kHz–10 MHz, and 10 MHz–100 MHz respectively, achieving <5 mΩ impedance across the full band when verified with a VNA.

Total capacitance budget: with DC-bias derating applied at 3.3 V bias, the 22 µF 1210 contributes ~20 µF effective, the 10 µF 0805 contributes ~8 µF at 3.3 V bias, and the 100 nF contributes full nominal. Combined effective capacitance is ~28 µF bulk—adequate for a 5 A load step with 50 mV droop target assuming <5 µH bus inductance.

Ripple and Transient Response

Output voltage ripple and load-transient response are the two primary metrics that validate your bulk-decoupling design. Ripple at steady state is dominated by ESR and ESL at the switching frequency: for the CL32B226KAJNNNE, ESR is typically 5–15 mΩ at 100 kHz (temperature- and frequency-dependent; read from the impedance curve, not estimated). ESL is typically 1–2 nH for a 1210 ceramic, giving an inductive impedance of 0.6–1.2 mΩ at 100 kHz—negligible compared to ESR at that frequency.

For a 500 kHz buck converter with 1 A peak-to-peak inductor ripple, the capacitor-contributed output ripple is: V_ripple_C = ΔI_L / (8 × f_sw × C_eff) = 1 / (8 × 500e3 × 20e-6) ≈ 12.5 mV, plus ESR contribution of ΔI_L × ESR = 1 × 0.010 = 10 mV, totaling ~22.5 mV—within a typical 50 mV specification. Stacking two CL32B226KAJNNNE units reduces the capacitive term to 6.25 mV.

Load transient response (10–90 % step, 0→5 A) requires sufficient bulk capacitance to limit droop during the converter's reaction time (typically 2–10 µs). Energy deficit: ΔV = ΔI × Δt / C_eff = 5 × 5e-6 / 20e-6 = 1.25 V—far exceeding a 50 mV target. This means the converter loop (not the cap) must respond in <800 ns, and the capacitor bridges only the initial microsecond. Increasing to 66 µF effective (3 × 22 µF derated) reduces droop to 0.38 V during 1 µs gap—still requiring fast converter response; confirm with a SPICE transient simulation using the vendor SPICE model.

Measure ripple and transient on the board with a 20 MHz bandwidth-limited oscilloscope probe at the capacitor pad (not at a remote test point), using a low-inductance ground spring, not a ground clip. Ground clip inductance alone (5–20 nH) can add 50–200 mV of apparent noise at 100 MHz, masking the true design performance.

Parameter	Tier 1 — Single 22 µF	Tier 2 — 22 µF + 10 µF + 100 nF	Tier 3 — 3× 22 µF + Filter Ladder
Effective capacitance at 3.3 V	~20 µF	~28 µF	~60 µF
Impedance at 1 MHz	~15 mΩ	~8 mΩ	~5 mΩ
Load step droop (5 A, 1 µs)	~250 mV	~180 mV	~83 mV
PCB area (approx.)	8 mm²	18 mm²	24 mm²
Best for	<3 A loads, benign flex environment	3–5 A loads, standard industrial	>5 A loads, low-droop requirements

Common Pitfalls and Troubleshooting

Pitfall 1 — Using nominal capacitance in the design budget. Engineers often write "22 µF decoupling" in a BOM note and calculate ripple from that number, but under 25 V bias the effective capacitance is 9–12 µF. Consequence: the ripple and droop calculations are 2× optimistic, and the board fails EMI or transient spec at system test. Correct approach: pull the C-V curve from the Samsung datasheet and use the value at your actual bias point. A simple design rule: never operate a 25 V-rated cap above 60 % of rated voltage (15 V) if you need >80 % of nominal capacitance.

Pitfall 2 — Ignoring the flex-termination requirement. Standard Sn-Ag termination on 1210 bodies cracks under PCB flexure during assembly or field handling. Consequence: intermittent shorts, leakage current, or parametric failure that is invisible in ICT but catastrophic in the field. Correct approach: use the soft-termination variant for any board that will be depaneled, hand-assembled, or mounted in a mechanically dynamic enclosure.

Pitfall 3 — Ground clip measurement artifacts. Probing the output cap with a standard oscilloscope ground clip adds 5–20 nH of inductance, which at 100 MHz adds 3–13 Ω of apparent impedance and makes a well-designed board look noisy. Consequence: engineers add unnecessary capacitance, worsening phase margin. Correct approach: use a low-inductance coaxial probe tip or a PCB-mounted SMA test point within 2 mm of the capacitor pad.

Pitfall 4 — Placing bulk cap far from the regulator pin. Every millimeter of trace between the cap pad and the IC pin adds ~1 nH/mm inductance on a typical 4-layer PCB. A 10 mm trace is 10 nH—at 10 MHz that is 628 mΩ of impedance, making the bulk cap nearly ineffective for fast transients. Correct approach: minimize distance; target ≤2 mm on high-current rails, ≤5 mm on rails below 2 A.

Pitfall 5 — Using X7R for ultra-low-frequency bulk energy storage without checking temperature range. X7R is stable from −55 °C to +125 °C per EIA-RS-198, but Class II capacitance still varies ±15 % over this range at 0 V. At rated voltage and 125 °C, compound derating can reach 65 %. Correct approach: for automotive or high-temperature industrial applications, choose a higher-voltage-rated part (50 V or 100 V) to reduce operating bias ratio, or switch to a Class I (C0G/NP0) multi-cap bank where tight tolerance is required at temperature extremes.

Frequently Asked Questions

What is the actual capacitance of the CL32B226KAJNNNE at 25 V bias? The Samsung Electro-Mechanics datasheet C-V curve shows the CL32B226KAJNNNE (22 µF, 25 V, X7R, 1210) retaining approximately 40–55 % of its nominal capacitance at 25 V DC bias, giving an effective capacitance of roughly 9–12 µF. This derating is due to the nonlinear permittivity of the X7R (barium titanate) dielectric under electric field. Always use the actual bias-point value from the C-V curve, not the 0 V nominal, when sizing your decoupling network.

How do I prevent mechanical cracking of the 1210 MLCC during assembly? Keep the capacitor at least 1.5 mm from panel-scoring lines, press-fit connector pads, and board edges. Use the soft-termination (flex-termination) variant for boards subject to depaneling stress, hand insertion, or field vibration. Follow Samsung's recommended reflow profile: peak 245–250 °C, cooling rate ≤3 °C/s. Rotate the capacitor 90° if it must be near a flex axis so terminations are parallel to the bend direction, reducing crack-initiation stress. Refer to IPC-9704 and JEDEC JESD22-B110 for qualification test procedures.

Can I replace the CL32B226KAJNNNE with a smaller 0805 10 µF cap for compact designs? Not directly—the 22 µF 1210 provides ~10–12× more bulk energy storage than a 10 µF 0805 at the same bias voltage (accounting for derating). If board area is constrained, stack two CL21B106KOQNNNE (10 µF, 0805, 16 V) in parallel on a lower-voltage rail, but note that 16 V-rated caps are not suitable for 25 V rails. For true 25 V applications, the 1210 package is typically the smallest practical option at 22 µF. Search for 25V 22uF MLCC alternatives to compare package options across vendors.

What is the self-resonant frequency (SRF) of the CL32B226KAJNNNE? The SRF of a 22 µF 1210 MLCC is typically 2–4 MHz, depending on the parasitic ESL (approximately 1–2 nH for 1210). Below the SRF the part behaves capacitively; above it, inductively. For switching regulators operating above 1 MHz, the 22 µF bulk cap provides limited high-frequency filtering on its own. Augment with a 100 nF X7R 0402 or 0603 cap (SRF ~50 MHz) in parallel to extend broadband coverage. This is why the three-tier decoupling ladder (22 µF + 10 µF + 100 nF) is the recommended approach for regulators above 500 kHz.

How many CL32B226KAJNNNE caps do I need for a 10 A, 3.3 V rail with 50 mV droop? For a 10 A load step with 50 mV droop and a converter response time of 2 µs: C_required = ΔI × Δt / ΔV = 10 × 2e-6 / 0.050 = 400 µF. With DC-bias derating at 3.3 V (~91 % of nominal retained), each cap contributes ~20 µF effective. You need approximately 20 capacitors in parallel—a large array that warrants evaluating higher-capacitance polymer-electrolytic or OS-CON alternatives for the bulk stage, with one or two CL32B226KAJNNNE for mid-frequency filtering. Use the FindMyChip quote tool to source a mixed BOM from verified distributors.

Conclusion

The Samsung CL32B226KAJNNNE is an excellent bulk-decoupling capacitor for 25 V and sub-25 V rails when the design accounts for three non-negotiable realities: DC-bias capacitance derating (plan for 9–12 µF effective at 25 V bias), 1210 mechanical fragility (use flex-termination and proper layout clearances), and placement discipline (within 2 mm of the regulator, low-inductance via pairs, no ground clips for measurement).

For most 3–5 A switching regulator designs, the three-tier ladder—one CL32B226KAJNNNE plus one CL21A106KOQNNNE and one CL21B104KBCNNNC—achieves <10 mΩ output impedance across DC to 10 MHz and covers the majority of industrial and consumer power rail requirements. For higher-current or lower-droop applications, parallel arrays with verified C-V derating budgets are the path forward.

Source all Samsung MLCC variants—including CL21B106KOQNNNE and the full CL32 series—through FindMyChip's network of 200+ verified distributors for competitive China pricing, 5-point anti-counterfeit authentication, and 24-hour RFQ response.