CL05B104KO5NNNC High-Frequency Decoupling: PDN Design Guide for 0402 100nF MLCC

Bottom Line: The CL05B104KO5NNNC is a 100 nF 16 V X7R 0402 MLCC from Samsung Electro-Mechanics that excels as a high-frequency bypass capacitor — but only when you account for its DC-bias derating (capacitance can drop 40–55% at 5 V on a 16 V-rated X7R), its mounted ESL (typically 0.3–0.8 nH in a 0402 footprint), and its self-resonant frequency (SRF ≈ 25–50 MHz depending on board stackup). Place it within 0.5 mm of the VCC pin, orient the terminations perpendicular to the current flow to minimize loop inductance, and always pair it with a bulk 10 µF 0805 MLCC such as the CL21B106KOQNNNE to cover both high-frequency and mid-frequency decoupling needs.

1. Why 100 nF MLCC Bypass Capacitors Are Both Essential and Misunderstood

A 100 nF bypass capacitor is the single most-used passive component on any modern PCB, yet it is routinely placed incorrectly or chosen without accounting for the real-world derating that determines its actual in-circuit capacitance. The CL05B104KO5NNNC (Samsung Electro-Mechanics, 0402, 100 nF, 16 V, X7R, ±10%) is a representative example of a high-quality MLCC in this category. Its compact 0402 body minimises parasitic inductance compared with 0603 or 0805 alternatives, making it the preferred choice for ICs operating above 50 MHz. Understanding the interaction between ESL, SRF, and DC-bias derating is mandatory before committing to a layout.

2. DC-Bias Derating: The Hidden Capacitance Loss

X7R class II ceramics lose a significant fraction of their rated capacitance under applied DC bias, an effect mandated by IEC 60384-21 but frequently overlooked in BOM-level design. For the CL05B104KO5NNNC at 16 V rating, applying 3.3 V DC typically reduces capacitance by 15–25%, while 5 V DC can reduce it by 35–50%. The practical consequence is that a nominal 100 nF capacitor may deliver only 50–65 nF at the operating voltage of a typical digital rail. Always verify the DC-bias curve from the Samsung MLCC catalog or the MLCC Finder tool before finalising the BOM, and uprate to 25 V or 50 V if you need the full 100 nF at 5 V supply rails.

Design guideline: if your supply is 3.3 V and you need ≥80 nF effective capacitance, choose the same 100 nF value in a 25 V rating, or select 220 nF at 16 V to compensate for derating.

3. Equivalent Series Inductance (ESL) and Mounted Parasitic Inductance

ESL is the dominant impedance limiter above the capacitor's SRF and determines how effectively the capacitor suppresses high-frequency noise. For a 0402 package the intrinsic ESL is approximately 0.4–0.6 nH (per JEDEC JEP147), but the total mounted ESL — including via inductance and PCB trace inductance — typically reaches 0.8–1.5 nH when standard via sizes and trace widths are used. Each 1 nH of inductance raises the impedance floor at 500 MHz by approximately 3 Ω, which is unacceptable for core-voltage rails of high-speed FPGAs or SoCs. To minimise mounted ESL:

1. Use reverse-geometry (wide-body) 0402 capacitors if available, or at minimum place standard 0402 parts with the termination axis perpendicular to the decoupling current path.
2. Use two vias directly under the capacitor pad lands — one via per terminal — rather than a single shared via.
3. Minimise trace length between the capacitor terminal and the IC VCC pin; target < 0.3 mm on inner layers.

The CL05B104KO5NNNC and CL05B103KB5NNNC (10 nF, 50 V, X7R, 0402) can be combined in parallel — 10 nF + 100 nF — to suppress both 100 MHz and 500 MHz noise bands simultaneously, as each value provides a distinct anti-resonance dip.

4. Self-Resonant Frequency and Effective Bypass Band

The SRF of the CL05B104KO5NNNC on a standard FR4 two-layer PCB is typically 25–40 MHz. Below the SRF the device behaves capacitively (impedance decreases with frequency, desirable); above the SRF it behaves inductively (impedance increases with frequency, undesirable). For ICs with switching frequencies or clock harmonics above 100 MHz, the 100 nF capacitor alone is insufficient. Pair it with a 10 nF 0402 in parallel (CL05B103KB5NNNC, SRF ≈ 80–120 MHz) to maintain low impedance across a broader decade. The resulting parallel combination provides an anti-resonance peak between the two SRFs, typically at a manageable impedance of 0.5–2 Ω when vias are optimised. Refer to TI Application Report SLVA493 for a worked example of multi-capacitor PDN impedance optimisation.

5. Power Distribution Network (PDN) Strategy

A robust PDN requires decoupling at three distinct frequency decades — bulk, mid-frequency, and high-frequency — each handled by different capacitor sizes.

PDN Tier	Frequency Range	Role	Recommended Part
Bulk	DC – 1 MHz	Charge reservoir, VRM transient	CL21B106KOQNNNE 10 µF 0805
Mid	1 – 50 MHz	IC transient current demand	CL21B104KBCNNNC 100 nF 0805
High-frequency	50 – 500 MHz	Clock edge bypass	CL05B104KO5NNNC 100 nF 0402

Place the 0402 bypass capacitor as close as possible to the IC power pin, then the 0805 mid-frequency capacitor in the second ring, then the 0805 bulk capacitor within 5 mm. This tiered placement mirrors the impedance requirements at each frequency band. For very high-speed designs (DDR5, PCIe Gen 5), also add buried capacitance planes and package-level decoupling, which are beyond the scope of this article.

Use a PDN simulation tool such as Cadence Sigrity PowerDC or the free PI-Analyst Lite to verify that the target impedance (often 10–50 mΩ for core rails) is maintained from 10 kHz to 1 GHz before finalising your layout.

6. Recommended Solutions

Solution A: Single-Capacitor Local Bypass (Simple Designs, ≤ 50 MHz Clock)

For low-complexity MCU boards where the core clock is below 50 MHz and supply is 3.3 V or 5 V, a single CL05B104KO5NNNC per VCC pin, placed within 0.5 mm, is sufficient. The 16 V rating provides an approximately 3× voltage margin from a 5 V rail (sufficient per IPC-2221A). Combine with one 10 µF 0805 MLCC per supply cluster.

Pros: minimal BOM, low cost, easy layout. Cons: limited effectiveness above 50 MHz, significant DC-bias derating at 5 V must be accepted or compensated.

Best for: STM32 Nucleo-style evaluation boards, sub-50 MHz microcontrollers, simple sensor nodes.

Solution B: Parallel 10 nF + 100 nF (Mid-Speed Designs, 50–200 MHz)

Pair the CL05B104KO5NNNC with a CL05B103KB5NNNC (10 nF, 50 V, X7R, 0402) at each IC VCC pin. The two capacitors provide overlapping impedance minima at 30–40 MHz and 90–120 MHz respectively, reducing the impedance floor to < 1 Ω across 10–200 MHz when via placement is optimised.

Parameter	CL05B104KO5NNNC	CL05B103KB5NNNC
Capacitance	100 nF	10 nF
Voltage Rating	16 V	50 V
SRF (mounted)	~30 MHz	~100 MHz
Package	0402	0402

Pros: broad-band coverage, still compact BOM footprint. Cons: requires careful anti-resonance management; the impedance peak between SRFs must be modelled.

Solution C: Full Three-Tier PDN (High-Speed Designs, > 200 MHz)

Implement the complete three-tier strategy: CL05B104KO5NNNC + CL05B103KB5NNNC at each pin, CL21B104KBCNNNC 0805 per power cluster, and CL21B106KOQNNNE 10 µF 0805 per supply domain. This mirrors the PDN architecture recommended in TI SLVA624 and Intel PDN Application Notes for high-speed digital designs.

Pros: lowest achievable impedance floor across the broadest frequency range; validated approach for FPGA, SoC, and DDR memory rails. Cons: higher component count and BOM cost; PCB real estate must accommodate multiple 0402 capacitors per pin.

Sourcing all four Samsung MLCC variants from a single channel ensures lot-to-lot consistency. You can search for these parts on FindMyChip or submit a consolidated quote request to compare pricing across 200+ verified distributors.

7. Common Pitfalls and Troubleshooting

Pitfall 1: Ignoring DC-Bias Derating Engineers order 100 nF capacitors and assume they deliver 100 nF in circuit. At 5 V on a 16 V X7R part, the effective value is 50–65 nF. The fix: check the vendor's DC-bias chart and derate the nominal capacitance before calculating PDN impedance.

Pitfall 2: Long Via Stubs Under Decoupling Capacitors Via stubs add series inductance that raises the SRF-referenced impedance. A 1 mm stub in FR4 adds ~0.7 nH, shifting the effective SRF downward. Use blind or buried vias, or back-drill stubs on high-speed designs above 3 GHz.

Pitfall 3: Placing Bypass Capacitors on the Far Side of the Board Placing capacitors on the back side of the PCB directly under the IC is often better than placing them on the front side 2–3 mm away. The current loop area and associated inductance scales with physical distance, not just trace length.

Pitfall 4: Using a Single Large Bulk Capacitor Instead of Multiple Small Ones A single 10 µF 1210 capacitor has much higher ESL (~2–3 nH) than four 2.2 µF 0402 capacitors in parallel (~0.3 nH combined). Distribute capacitance across smaller packages to minimise ESL at the package level.

Pitfall 5: Neglecting Temperature-Dependent Capacitance Shift X7R is rated stable from −55°C to +125°C with ≤±15% capacitance change (IEC 60384-22). However, at the 55 V and +85°C corner simultaneously, real-world capacitance can drop an additional 10–20% beyond the DC-bias loss. Design the PDN with adequate margin for worst-case temperature plus DC-bias combined derating.

8. Frequently Asked Questions

Q: What does the "X7R" dielectric mean for the CL05B104KO5NNNC? X7R is an EIA Class II ceramic designation indicating a temperature coefficient of ±15% capacitance change from −55°C to +125°C. It is the standard choice for general-purpose bypass and filtering because it offers a good balance between volumetric efficiency and thermal stability. Avoid Y5V or Z5U in precision or power-supply applications since their capacitance can change by −80% at temperature extremes.

Q: How many CL05B104KO5NNNC capacitors do I need per IC? As a rule of thumb, place one 100 nF bypass capacitor per VCC/VDD power pin on the IC. For high-pin-count BGA devices with multiple power pins, one 0402 bypass capacitor per power-pin pair is common practice. Always cross-check with the IC datasheet's recommended decoupling section, which often specifies exact capacitor values and placement distances.

Q: Can I replace the CL05B104KO5NNNC with a 10 µF capacitor for better decoupling? Larger values are better at low frequencies but worse at high frequencies because the SRF shifts lower and ESL increases for the same package size. A 10 µF 0402 is not available in reliable supply; the nearest common part is 10 µF 0805. Use the CL21B106KOQNNNE 10 µF 0805 as a bulk supplement, not a replacement, for the 100 nF 0402 at each pin.

Q: How do I verify the SRF of the CL05B104KO5NNNC in my specific board stackup? Use a vector network analyser (VNA) in S11/S21 mode with a dedicated 2-port capacitor measurement fixture such as the Picotest J2101A. Mount a sample capacitor on the actual PCB stackup you plan to use and sweep from 1 MHz to 1 GHz. The impedance minimum marks the SRF. This measurement takes fewer than 10 minutes and eliminates the uncertainty from datasheet SRF specifications that assume an ideal test fixture.

Q: Where can I find competitive pricing for the CL05B104KO5NNNC in quantity? FindMyChip aggregates real-time pricing from 200+ verified distributors, many of which specialise in Samsung Electro-Mechanics MLCC. Submit a quote request or use the parts search to compare per-unit pricing at your target quantity. Domestic China distributors often offer competitive pricing on Samsung MLCC, especially for quantities above 10,000 pieces.

Conclusion

High-frequency decoupling with the CL05B104KO5NNNC requires understanding three interdependent physical effects: DC-bias derating, mounted ESL, and self-resonant frequency. Used as a single-tier bypass capacitor at low clock speeds it is a cost-effective, well-characterised solution. For high-speed digital designs above 100 MHz, combine it with a 10 nF 0402 peer and a 10 µF 0805 bulk capacitor to build a three-tier PDN that meets sub-50 mΩ target impedance requirements across the full bandwidth. Always simulate or measure the PDN before tape-out to avoid costly board respins.

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