CDCE913PWR vs CDCE925PWR vs CDCE906: Which TI Clock Synthesizer Is Right for Your Design?

Bottom Line: If you need a simple single-PLL clock synthesizer for one or two outputs, the CDCE913 delivers at the lowest cost and smallest footprint. Step up to the CDCE925 when you need two independent PLLs or five outputs, and consider the CDCE906 when your design demands spread-spectrum modulation for EMI compliance.

Introduction

Texas Instruments' CDCExx family of programmable VCXO-based clock synthesizers covers a wide range of multi-output clocking needs. Engineers frequently land on three sibling parts — the CDCE913PWR, the CDCE925PWR, and the CDCE906 — when searching for a programmable, low-jitter clock source for FPGAs, DSPs, video processors, or high-speed serial interfaces. All three accept a reference crystal or clock input and synthesize one or more output frequencies using on-chip PLL loops. The differences in PLL count, output count, spread-spectrum support, and price can make the selection non-obvious. This comparison article walks through the key axes so you can make the right call before committing to a layout.

Quick Comparison Table

Parameter	CDCE913PWR	CDCE925PWR	CDCE906PW
PLL Count	1	2	1
Output Count	3	5	6
Max Output Frequency	230 MHz	230 MHz	200 MHz
Spread-Spectrum	No	No	Yes (±0.5 % or ±1 %)
Output Voltage	2.5 V / 3.3 V LVCMOS	2.5 V / 3.3 V LVCMOS	3.3 V LVCMOS
VDD Supply	2.5 V or 3.3 V	1.7 V – 1.9 V (core) / 2.5 V or 3.3 V I/O	3.3 V
Configuration Interface	I2C / EEPROM	I2C / EEPROM	I2C / EEPROM
Package	TSSOP-16	TSSOP-16	TSSOP-16
Typical Volume Price	~$1.50	~$2.20	~$2.00

Note: Prices are indicative volume estimates. Use the FindMyChip quote tool for live distributor pricing across 200+ verified sources.

Detailed Analysis

1. PLL Architecture and Output Flexibility

The CDCE913 integrates a single fractional-N PLL. It synthesises three output clocks, all phase-locked to the same reference — meaning you cannot independently set two output frequencies that require incommensurable ratios. For many single-domain designs (one FPGA fabric clock plus two peripheral clocks derived from the same base frequency) this is sufficient, and the single-PLL topology contributes to lower power and a smaller die area.

The CDCE925 adds a second independent PLL. With five configurable outputs, you can assign two completely independent frequency domains, making it well suited for SoC designs that combine a high-speed DDR memory interface (e.g., 400 MHz) with an Ethernet SGMII clock (125 MHz) that shares no common integer relationship with the memory clock. The two PLLs can lock to the same crystal reference or to separate inputs.

The CDCE906 also uses a single PLL but offers six outputs. Its distinguishing feature is spread-spectrum clock generation (SSCG): the output frequency is intentionally modulated (center-spread or down-spread, typically ±0.5 % or ±1 %) at a programmable rate. SSCG is the primary tool for reducing radiated EMI on clocks that would otherwise create a sharp spectral spike at the CISPR 32 measurement frequency.

2. Frequency Planning and Fractional Dividers

All three devices use I2C-programmable PLL multiplier and divider registers, and all support pre-programming into an internal EEPROM for standalone (I2C-less) operation after power-up. The CDCE913 and CDCE925 share the same fractional-N PLL core (VCO range approximately 80–230 MHz output), with Y-dividers on each output path allowing non-integer ratios.

The CDCE906 targets slightly lower maximum frequencies (200 MHz) but adds the SSCG modulation engine. If your design stretches to 230 MHz outputs, the CDCE906 is out of scope; otherwise, the three devices are broadly interchangeable on raw frequency capability.

3. Power Consumption

The CDCE913 operates from a single 2.5 V or 3.3 V supply, making power budgeting straightforward. Typical active current is around 20–30 mA depending on output load. Its single-PLL architecture means no second charge pump running continuously.

The CDCE925 splits the supply rail: the PLL core runs at 1.7–1.9 V while the output buffers use 2.5 V or 3.3 V. This lowers the internal analog noise floor but requires your board to provide a clean LDO or DCDC output at 1.8 V. Total active current is higher — roughly 35–50 mA across both rails — reflecting the dual-PLL hardware.

The CDCE906 runs from a single 3.3 V supply only and draws approximately 30–40 mA active. Designs targeting 2.5 V I/O throughout cannot use the CDCE906 directly without level translation on the output pins.

4. Spread-Spectrum and EMI

For consumer and industrial products that must pass FCC Part 15 Class B or CISPR 32 conducted/radiated emission tests, a clock synthesizer that continuously spreads its output frequency is often more cost-effective than adding shielding, ferrite beads, or board-level layout workarounds. The CDCE906 is the only member of this trio to include SSCG. If your product has EMI requirements and the clock domain in question is a significant radiator (long traces, poor ground plane, driving a connector), the CDCE906's EMI advantage may outweigh the CDCE913 or CDCE925's lower price or higher output count.

5. Ecosystem, Tools, and Second-Source Availability

All three parts are configurable with TI's CDCE-GUI Windows utility. Configuration files generated by the GUI can be written to the on-chip EEPROM via I2C during production programming. The I2C register map is consistent across the family, so migrating a firmware driver from one part to another requires only minor register updates.

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6. Cost and Availability

The CDCE913 is the most cost-efficient option at volume, typically running around $1.50 per unit in 1k+ quantities. The CDCE925 carries a roughly 40–50 % premium, reflecting the dual-PLL integration. The CDCE906 sits between the two in price and is slightly less common in distribution, so lead-time risk is marginally higher. All three ship in tape-and-reel (PWR suffix = 2000 units per reel) and tube form, and all carry the TSSOP-16 footprint, making PCB migration between siblings straightforward.

Use Case Recommendations

Choose the CDCE913PWR when:

• Your design needs at most three output clocks, all derived from the same base frequency.
• Cost or power budget is the primary constraint.
• 2.5 V or 3.3 V single-supply operation is required.
• EMI spread-spectrum is not a requirement.

Choose the CDCE925PWR when:

• You need two independent frequency domains on a single device (e.g., DDR + Ethernet, or two independent FPGA clock domains with incommensurable frequencies).
• Five output channels are needed.
• You can supply a clean 1.8 V rail for the PLL core.

Choose the CDCE906PW when:

• Radiated EMI reduction is a design requirement (FCC, CISPR, CE mark).
• Six outputs cover your distribution needs.
• Your I/O standard is exclusively 3.3 V LVCMOS.

Frequently Asked Questions

Can I swap a CDCE913PWR for a CDCE925PWR on the same PCB? Both use the same TSSOP-16 package and pin-compatible footprint, and both share the I2C register programming model. The CDCE925 requires an additional 1.8 V supply pin, so a direct drop-in replacement without board modification is not possible. A minor schematic change (adding an LDO for the core supply) and a firmware register update are needed.

Does the CDCE906 require an external crystal, or can it accept a LVCMOS clock input? The CDCE906 accepts both a crystal (fundamental mode, 8–25 MHz typical) connected across the XTAL pins and a single-ended LVCMOS clock input driven into the CLK pin. Consult the datasheet reference schematic for input termination values — incorrect loading can degrade jitter significantly.

How do I program the EEPROM for standalone operation? Use TI's free CDCE-GUI software to generate the register configuration. Connect the device to a PC via an I2C adapter (e.g., TI's USB-I2C bridge dongle), write the configuration to the volatile registers first to verify output frequencies on the bench, then burn to EEPROM. After power cycling, the device starts in the pre-programmed state without I2C intervention.

Conclusion and Next Steps

The CDCE913PWR, CDCE925PWR, and CDCE906 address different points on the complexity-vs-cost curve. Single-domain three-output designs belong on the CDCE913. Multi-domain designs with two independent frequency plans belong on the CDCE925. Designs where EMI compliance drives the clock architecture belong on the CDCE906.

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