CDCE913PWR Programmable Clock Synthesizer Design Guide

Bottom Line: The CDCE913PWR is a single-PLL, triple-output VCXO clock synthesizer from Texas Instruments that supports output frequencies up to 230 MHz from a 10–800 MHz input reference. For most embedded and communications designs, configure the PLL feedback divider to keep VCO frequency in the 80–230 MHz window, set LVCMOS output levels for the target voltage rail (2.5 V or 3.3 V), and program the device over I²C using TI's TICS Pro tool before committing to final firmware. Those three decisions — VCO range, output voltage, and I²C programming sequence — determine 90% of first-pass success.

Overview of the CDCE913PWR

The CDCE913PWR is a programmable 1-PLL VCXO clock synthesizer with three LVCMOS outputs designed for cost-sensitive embedded systems that require multiple synchronized clocks from a single crystal reference. It targets consumer electronics, industrial automation, communications infrastructure, and test equipment where clean, low-jitter clocks drive FPGAs, DSPs, and high-speed serial interfaces.

Key specifications at a glance:

• Input reference: 10–800 MHz (crystal or clock input)
• VCO output range: 80–230 MHz (internal PLL)
• Output count: 3 independent LVCMOS outputs (Y1, Y2, Y3)
• Output voltage: 2.5 V or 3.3 V (VDDOUT-selectable)
• I²C address: configurable via A0/A1 pins
• Package: 16-pin TSSOP (PWR suffix = tape-and-reel)
• Operating temperature: –40 °C to +85 °C (industrial)
• Supply: 1.8 V core (VDDA), 2.5 V or 3.3 V output (VDDOUT)

The CDCE913PWR belongs to TI's CDCE9xx family, which spans 1-PLL to 4-PLL variants. For designs requiring more outputs or multiple independent PLLs, the CDCE949PWRG4 provides four PLLs and eight outputs while sharing the same I²C programming model, reducing migration risk.

Design Consideration 1 — VCO Frequency and PLL Divider Selection

The CDCE913PWR's internal VCO must operate between 80 MHz and 230 MHz for phase-lock stability. Program the feedback divider (N) and input pre-divider (P) so that VCO_freq = Fref × N / P falls within this window. Choosing a VCO frequency outside this range forces the PLL into an unspecified operating region and causes cycle-to-cycle jitter to rise dramatically — often above 100 ps RMS, which violates DDR3 and PCIe Gen 1 timing budgets.

Recommended practice:

1. Start with your desired output frequency (e.g., 100 MHz for a DDR reference).
2. Select the output post-divider M so that VCO_freq = Fout × M lands in the 80–230 MHz band.
3. Adjust N and P such that VCO_freq = Fref × N / P matches step 2 within ±50 ppm.
4. Use TI's TICS Pro or the CDCE913 Register Programming Guide (SCAS878) to encode N, P, M into registers 0–5.

A common mistake is choosing P = 1 (no pre-division) when Fref > 80 MHz, which pushes the VCO above 230 MHz if N > 1. Always pre-divide high-frequency crystal inputs (e.g., 25 MHz TCXO sources typically need P = 1, N = 4 to reach 100 MHz VCO — which is valid).

Design Consideration 2 — Output Voltage and Load Management

VDDOUT sets the LVCMOS swing for all three outputs simultaneously; mixing 2.5 V and 3.3 V loads on the same device is not supported. Connect VDDOUT to the rail that drives the most power-critical load — typically the FPGA I/O bank — and use level shifters or series termination for minority loads on a different rail.

Each output can drive one LVCMOS load directly. For fanout > 1, insert a low-skew clock buffer (e.g., CDCLVD1204 for LVDS fanout, or SN74BCT125 for LVCMOS). The CDCE913PWR output impedance is 25 Ω typical; use series termination resistors of 22–33 Ω on traces longer than 50 mm at 100 MHz to prevent reflections (rise time ~2 ns, electrically long threshold at ~100 mm).

Do not exceed the 24 mA maximum output current per pin. Driving multiple loads in parallel without buffering violates this limit and causes waveform degradation visible on a 1 GHz oscilloscope as ringing above the datasheet VOH spec.

Design Consideration 3 — I²C Programming and Device Configuration

The CDCE913PWR boots from an internal ROM with default register values; all production systems must reprogram the device at power-on via I²C or use a one-time programmable (OTP) option. The I²C address is set by the A0 and A1 pins: tie to VDDIO or GND to select one of four addresses (0x68 – 0x6B). Confirm no I²C address conflict with onboard RTC, EEPROM, or power-management ICs before PCB layout sign-off.

Register programming follows SCAS878: byte 0 is the sub-address (register pointer), bytes 1–N are sequential register writes. The PLL lock time is typically 1–10 ms after I²C write completes, depending on Fref. Your firmware must poll the PLL_LOCK bit (Register 0, bit 7) or add a 10 ms fixed delay before releasing downstream clocks to avoid clock glitches during boot. This is a frequently missed requirement — omitting the lock check causes intermittent FPGA configuration failures that are difficult to reproduce.

For volume production, TI offers the CDCE913PWR with an OTP register bank programmed at the factory. Submit the register file via TI's OTP ordering process to eliminate I²C firmware dependency and reduce BOM (no configuration EEPROM required). This is particularly valuable in cost-sensitive or security-sensitive designs.

Design Consideration 4 — Power Supply Decoupling and PCB Layout

The CDCE913PWR uses a split-supply architecture: VDDA (1.8 V) powers the PLL analog core, and VDDOUT powers the output drivers. Both rails require separate decoupling to minimize supply noise coupling into the VCO. Recommended decoupling:

• VDDA: 100 nF X5R ceramic + 10 µF bulk electrolytic, placed within 1 mm of the VDDA pin.
• VDDOUT: 100 nF X5R ceramic per output pair, placed within 2 mm of the device.
• VDDA ground return must connect directly to the analog ground plane — do not route through digital ground.

Place the CDCE913PWR within 25 mm of the crystal or TCXO reference to minimize input trace inductance. Use a ground guard ring around the crystal to suppress parasitic coupling. Input trace impedance is not critical (the input is high-impedance CMOS), but keep it below 50 mm to avoid radiating at reference frequency. Route output clocks on 50 Ω controlled impedance traces; avoid parallel routing with high-speed data lanes for more than 20 mm.

Design Consideration 5 — Crystal Reference Selection

The CDCE913PWR accepts a parallel-resonant crystal or an external clock source on the XTAL_IN pin. For crystal mode, load capacitance must match the crystal's CL spec (typically 12–18 pF): calculate PCB trace capacitance (~1–2 pF for a short trace) and subtract from the crystal's CL to determine external load caps (CL_ext = 2 × (CL – Ctrace)). Using wrong CL shifts crystal frequency by 10–50 ppm, degrading PLL output accuracy.

Crystal frequency should be in the range where 10 ≤ Fxtal ≤ 200 MHz. Practical designs commonly use 25 MHz or 48 MHz TCXO sources for communications applications where ±2.5 ppm frequency accuracy is required (e.g., USB 2.0 full-speed, Ethernet synchronous mode). For lower accuracy applications, a standard ±50 ppm 25 MHz crystal is sufficient. Refer to TI Application Report SLAA322 for crystal selection and oscillator startup analysis.

Recommended Solutions

Solution A — CDCE913PWR Standard I²C-Programmed Design

Best for: FPGA and DSP boards where a host MCU handles device initialization.

This is the most common deployment: the CDCE913PWR sits alongside an MCU on the same I²C bus. At startup, the MCU writes a pre-computed 8-byte register file to configure PLL, dividers, and output enables within 5 ms of power-on.

Recommended part: CDCE913PWR (16-pin TSSOP, tape-and-reel)

Pros:

• Full flexibility — change output frequencies via firmware without hardware changes.
• No OTP ordering lead time.
• Compatible with standard I²C host libraries (Linux kernel clock driver available for CDCE913).

Cons:

• Firmware must handle PLL lock timeout and I²C error recovery.
• Requires I²C bus access during early boot — conflicts with shared-bus designs that use I²C for power sequencing.

Applicable when: prototyping, low-volume production, or designs requiring runtime frequency switching.

Solution B — CDCE913PWG4 OTP-Programmed for High Volume

Best for: High-volume consumer or industrial products where BOM simplicity and boot determinism are critical.

The CDCE913PWG4 shares the same die but can be ordered with OTP registers pre-burned to your register file. The device boots directly into the programmed frequency without any I²C transaction.

Pros:

• No firmware overhead for clock configuration.
• Eliminates external configuration EEPROM.
• Reduces boot time by 5–15 ms (no I²C sequence).

Cons:

• OTP is one-time — requires finalized register file before volume orders.
• Minimum OTP order quantities apply (check TI for current MOQ).
• Design changes require a new OTP register file and re-qualification.

Applicable when: volume > 5 K units/year, bootloader is locked, or firmware update to clock config is not feasible in the field.

Solution C — CDCE949PWRG4 for Multi-PLL Applications

Best for: Designs requiring four independent clock domains (e.g., mixed-signal boards with audio, USB, Ethernet, and display clocks).

The CDCE949PWRG4 extends the CDCE913 architecture to four independent PLLs and eight LVCMOS outputs, all I²C-programmable with the same register model. It is pin-compatible with CDCE913 in the TSSOP package, enabling a straight upgrade path.

Parameter	CDCE913PWR	CDCE949PWRG4
PLL count	1	4
Output count	3	8
Max output freq	230 MHz	230 MHz
I²C config	Yes	Yes
Package	TSSOP-16	TSSOP-24
Supply voltage	1.8 V / 2.5–3.3 V	1.8 V / 2.5–3.3 V

Applicable when: more than one independent PLL is needed, or output count exceeds three.

Common Pitfalls and Troubleshooting

Pitfall 1 — VCO Out-of-Range After Register Write

Symptom: Output clock is missing or at wrong frequency after I²C configuration. Cause: N/P ratio pushes VCO below 80 MHz or above 230 MHz. Fix: Use TICS Pro to validate the register file before firmware commit. The tool flags out-of-range VCO frequencies in its "Check" function. Never write registers derived solely from manual calculation without tool validation.

Pitfall 2 — PLL Never Achieves Lock

Symptom: PLL_LOCK bit remains 0 indefinitely; outputs toggle but at wrong frequency. Cause: Crystal load capacitance mismatch causing reference frequency error > 500 ppm, which exceeds the PLL acquisition range. Fix: Verify crystal CL spec and PCB stray capacitance. Swap to a TCXO clock input for bench debugging to isolate whether the issue is crystal oscillator startup or PLL configuration.

Pitfall 3 — Excessive Output Jitter (> 50 ps RMS)

Symptom: High-speed serial link eye diagram shows degraded margin; BER increases. Cause: VDDA supply noise above 5 mV RMS coupling into the PLL VCO. Fix: Improve VDDA filtering: add a ferrite bead (600 Ω at 100 MHz, e.g., BLM18PG601SN1D) in series with the VDDA supply, with 100 nF + 10 µF downstream. Separate VDDA ground return from digital ground return.

Pitfall 4 — I²C Write Succeeds but Device Ignores Registers

Symptom: Registers read back correctly but outputs remain at default frequency. Cause: Missing software reset after register write. The CDCE913 requires a device reset (Register 0, bit 6 write-then-clear) to latch new PLL parameters. Fix: Issue a software reset after the last register write; wait 10 ms for PLL relock before releasing output clock enables.

Pitfall 5 — Ground Bounce on Output Transitions

Symptom: Other devices on the board reset or behave erratically at clock startup. Cause: All three LVCMOS outputs switch simultaneously, causing a ground bounce transient on the digital ground plane. Fix: Enable outputs one at a time via the OE (output enable) register bits with 1–5 ms inter-output delay. This reduces simultaneous switching current from 3× to 1× per transition.

FAQ

Q: What is the maximum output frequency of the CDCE913PWR? A: The CDCE913PWR supports output frequencies from less than 1 MHz up to 230 MHz, constrained by the internal VCO range of 80–230 MHz and the programmable post-divider. The output divider can generate sub-MHz outputs from a 80 MHz VCO by setting high division ratios. For outputs above 230 MHz, consider TI's CDCE62005 or LMK04800 series.

Q: Can the CDCE913PWR be used as a spread-spectrum clock generator? A: No — the CDCE913PWR does not support spread-spectrum modulation. It is a fixed-frequency synthesizer. For applications requiring spread-spectrum (e.g., EMI reduction in USB or SATA host controllers), use TI's CDCS501 or a dedicated spread-spectrum clock IC such as the Cypress CY25701.

Q: How do I calculate the I²C register values without TICS Pro? A: TI Application Report SCAS878 includes the full register map and calculation formulas. The PLL configuration requires computing P (input pre-divider, 1–32), N (feedback divider, 1–4095), and M (output post-divider, 1–511) such that VCO_freq = Fref × N / P and Fout = VCO_freq / M. Both VCO_freq must satisfy 80 ≤ VCO_freq ≤ 230 MHz. TICS Pro automates this search, but the formulas are tractable by spreadsheet for a fixed Fref and Fout pair.

Q: Is the CDCE913PWR AEC-Q100 qualified? A: The standard CDCE913PWR is rated for industrial temperature (–40 °C to +85 °C) but is not AEC-Q100 qualified. For automotive clock synthesizers, TI offers the CDCM6208 and CDCM7005 families with AEC-Q100 Grade 1 qualification. Check the current TI product page for the latest automotive portfolio.

Q: How many CDCE913PWR devices can share one I²C bus? A: Up to four devices can coexist on one I²C bus by configuring the A0 and A1 pins to select unique addresses (0x68, 0x69, 0x6A, 0x6B). Beyond four, use an I²C multiplexer (e.g., TCA9548A) to expand addressable clock synthesizers while keeping each CDCE913PWR at a unique address on its sub-bus.

Conclusion

The CDCE913PWR is a well-characterized, I²C-programmable clock synthesizer that covers most embedded and communications use cases requiring one to three synchronized LVCMOS clocks below 230 MHz. Successful first-pass silicon comes down to three practices: keep the VCO inside 80–230 MHz, decouple VDDA independently from digital supplies, and poll the PLL_LOCK bit before releasing output clocks.

For production sourcing of the CDCE913PWR, CDCE913PWG4, and CDCE949PWRG4, FindMyChip connects you to 200+ verified distributors with real-time stock and competitive pricing. Request a quote for volume inquiries or search our catalog to compare availability across the CDCE9xx family today.