AD7607BSTZ Application Note: 8-Channel Simultaneous Sampling ADC Design Guide

Bottom Line: The AD7607BSTZ is an 8-channel, 14-bit simultaneous-sampling ADC from Analog Devices that targets industrial data acquisition, motor control, and power monitoring applications. For best results: (1) supply AVCC and DVCC from separate regulated 5 V and 3.3 V rails to achieve the datasheet's −94 dB THD spec; (2) use a dedicated analog ground plane with a single star-point connection to the digital ground; (3) drive each analog input through a matched RC anti-aliasing filter (e.g., 33 Ω + 47 nF, −3 dB at ~100 kHz) to suppress switching noise above the 200 kSPS throughput rate.

What Is the AD7607BSTZ?

The AD7607BSTZ is the 48-lead LQFP variant of Analog Devices' AD7607, an 8-channel, 14-bit simultaneous-sampling SAR ADC with an integrated 5 V reference, input amplifiers, and SPI/parallel interface. Simultaneous sampling eliminates the channel-to-channel phase error that haunts multiplexed architectures — a critical property when measuring three-phase currents, differential voltages, or any signals where phase alignment matters. The device accepts true bipolar analog inputs of ±10 V or ±5 V, selectable via a hardware pin, making it directly compatible with most industrial sensor outputs without a front-end attenuation stage.

Key headline specifications:

Resolution: 14 bits
Channels: 8 simultaneous
Throughput: up to 200 kSPS per channel
Input range: ±10 V or ±5 V (pin-selectable)
Interface: SPI (up to 23 MHz SCLK) and parallel bus
Supply: AVCC = 5 V ±5%, DVCC = 2.7–5.25 V
Package: 48-lead LQFP (B-grade, −40 °C to +85 °C)

Design Consideration 1 — Power Supply Decoupling and Regulation

Clean supply rails are the single largest determinant of achievable SNR in any precision ADC design. The AD7607BSTZ datasheet specifies a typical SNR of 83 dB, but every 10 mV of supply noise can degrade this by 1–2 dB. Analog Devices recommends placing 10 µF tantalum caps in parallel with 100 nF ceramic X5R caps at each AVCC and DVCC pin, located within 1 mm of the package. Use a dedicated low-noise LDO for the AVCC rail — a switching regulator needs at least a 10 MHz second-order LC post-filter to meet the <1 mVpp ripple budget. The DVCC rail is more forgiving but should still be separated from the digital logic rail by a 1 Ω ferrite bead (rated ≥500 mA) to attenuate high-frequency logic switching transients.

The internal reference (2.5 V output buffered to produce 5 V full-scale) is trimmed to ±5 ppm/°C. If you need better temperature stability, bypass REFIN/REFOUT with a 10 µF + 100 nF network and optionally overdrive REFIN with an external reference such as the ADR4550. Overdriving the reference does not void the SNR specification as long as the source impedance is <1 Ω at 200 kSPS.

Design Consideration 2 — Analog Input Interface and Anti-Aliasing

The AD7607BSTZ's on-chip input amplifiers present a 1 MΩ input impedance and handle bipolar signals up to ±10 V, but the amplifier input stage produces a switched-capacitor load during sampling that requires source impedance matching. Each analog input should be driven through a series resistor (22–47 Ω typical) to isolate the driving amplifier from the capacitive kick, followed by a shunt capacitor (10–100 nF) to form a first-order anti-aliasing filter. For a 200 kSPS update rate, the Nyquist frequency is 100 kHz; an RC pole at 48 kHz (33 Ω, 100 nF) provides >40 dB alias suppression at the imaging frequency. Industrial sensors with bandwidth above 10 kHz may benefit from a second-order active anti-aliasing filter using a precision op-amp (e.g., AD8221 instrumentation amplifier ahead of a Sallen-Key LPF).

Avoid placing the RC components farther than 5 mm from the AVCC decoupling caps — longer traces pick up radiated switching noise from nearby FETs or inductors. The PCB layout should route analog input traces on the analog ground plane only, with no digital signal trace crossing underneath.

Design Consideration 3 — Grounding and PCB Layout

A split ground plane strategy — analog copper poured on one layer, digital on another, joined at a single star point under the AGND pin — achieves the cleanest conversion performance. The AD7607BSTZ has dedicated AGND and DGND pins; connect AGND to the analog plane and DGND to the analog plane as well (not the digital plane), per the AD7607 datasheet layout recommendations. All high-speed digital signals (SCLK, CS, RD, BUSY) should be routed on the digital plane and cross the analog plane boundary only through the package ball. Use a ground-referenced crystal oscillator for the CONVST source clock; clock jitter above 100 ps RMS degrades effective number of bits (ENOB) at full throughput.

Via stitching around the ADC island with ground vias at every 2–3 mm creates an effective Faraday cage for the sensitive analog section. If the PCB uses a 4-layer stackup, place the signal layers on layers 1 and 4 and the solid ground plane on layer 2 — this maximizes the referenced return path for all analog traces.

Design Consideration 4 — Digital Interface Selection: SPI vs Parallel

The AD7607BSTZ supports both SPI (daisy-chain capable) and parallel 8-/16-bit bus modes, selectable at power-on via the PAR/SER/BYTE SEL pin. SPI mode at 23 MHz SCLK can read all 8 channels in 4.8 µs — comfortably within the minimum sample period of 5 µs at 200 kSPS. Parallel mode reduces read time to under 2 µs by clocking out two 8-bit bytes per channel, beneficial in FPGA-coupled designs where bus bandwidth is plentiful. For microcontroller designs with a single SPI peripheral, daisy-chaining two AD7607BSTZ devices doubles channel count to 16 without additional CS lines, since the DOUT/RDY pin can be connected serially to the SDI of the second device.

Regardless of interface choice, the BUSY signal timing is critical: CONVST↑ triggers conversion; conversion completes in ≤4 µs (B-grade at 25 °C); BUSY↓ signals valid data. Do not assert RD or SCLK until BUSY goes low. In FPGA implementations, synchronize BUSY through two flip-flops on the digital clock domain before using it as a read-enable to avoid metastability.

Design Consideration 5 — Throughput, Oversampling, and OSR Settings

The AD7607BSTZ's hardware oversampling ratio (OSR) pin trio (OS0, OS1, OS2) allows on-chip averaging from ×1 (200 kSPS, 14-bit) to ×64 (3.125 kSPS, up to 17-bit ENOB) without external DSP. Each doubling of the OSR improves ENOB by ~0.5 bits through noise averaging. At OSR=×4, throughput drops to 50 kSPS but ENOB increases to ~15.5 bits — a good compromise for 50 Hz/60 Hz power monitoring applications where measurement bandwidth above 1 kHz is unnecessary. JEDEC-standard voltage regulators and IEC 61000-4-3 EMC standards align well with the ×4 or ×8 OSR setting for grid-tied power monitoring.

At maximum OSR (×64), the part meets the accuracy requirements of IEC 61010-1 Class 1 power metering. Always match the OSR to the sensor bandwidth: a 10 kHz vibration sensor cannot benefit from ×64 oversampling because its signal content falls above the averaging window's Nyquist band.

Solution	Part	Channels	Resolution	Throughput	Best For
Solution A: Full 8-CH 14-bit	AD7607BSTZ	8	14-bit	200 kSPS	Motor control, industrial DAQ
Solution B: 8-CH, tape/reel	AD7607BSTZ-RL	8	14-bit	200 kSPS	High-volume production
Solution C: 4-CH 16-bit	AD7606BSTZ-4	4	16-bit	200 kSPS	High-accuracy instrumentation

Common Pitfalls and Troubleshooting

Pitfall 1 — Floating OSR pins cause random oversampling mode

If OS0–OS2 pins are left unconnected, internal pull-downs select OSR=×1, but any noise coupling can cause the device to latch a different OSR on power-up. Always tie OS0–OS2 explicitly to DVCC or GND through 10 kΩ pull resistors. Symptom: throughput varies unpredictably between resets. Fix: add explicit pin-strap resistors and verify OSR setting in firmware by cross-checking conversion time against BUSY pulse width.

Pitfall 2 — Simultaneous CONVST assertion with SPI read

Asserting CONVST while a SPI read is in progress can corrupt the output shift register and produce bit errors on the subsequent sample. Symptom: occasional single-LSB glitches or −1 code errors at high throughput. Fix: gate CONVST through firmware so it is only toggled at least 50 ns after CS↑ (end of SPI transaction), as specified in the AD7607 timing diagram (t6 parameter).

Pitfall 3 — RESET held too short after power-up

The RESET pulse must be held high for at least 50 ns and must occur after AVCC and DVCC are within regulation. Applying RESET before AVCC stabilizes can leave the internal DAC reference in an unknown state, producing static offset errors of several LSBs. Fix: use a dedicated power-on reset IC or MCU GPIO with a 100 µs delay after both supply rails exceed their UVLO threshold.

Pitfall 4 — Mixing AGND and DGND at multiple points

Connecting AGND and DGND at more than one point creates ground loops that modulate the analog input with digital switching currents. A 50 mA SPI bus switching at 20 MHz can inject >1 mVpp onto the AGND plane through a 20 mΩ trace resistance, degrading SNR by 3–5 dB. Fix: join AGND and DGND at exactly one star point, as shown in the AD7607 datasheet evaluation board layout.

Pitfall 5 — AVCC LDO output not adequately bypassed

LDOs with >10 mΩ output impedance at 1 MHz are insufficient for AVCC — the ADC's on-chip PGA draws impulsive currents during sampling that ring the LDO rail. Symptom: SNR 5–10 dB below typical at higher throughput rates. Fix: add a 10 µF low-ESR bulk capacitor (X5R ceramic or tantalum) within 5 mm of the AVCC pin, combined with the standard 100 nF close-mount cap.

FAQ

Q: Can the AD7607BSTZ be powered from a single 3.3 V supply?

No. The AVCC pin requires 5 V ±5% to bias the internal input amplifiers and reference. Only DVCC is compatible with 3.3 V logic. In a 3.3 V system, generate 5 V for AVCC using a low-noise boost converter (e.g., TPS61040) followed by a 5 V LDO, and connect DVCC directly to the 3.3 V digital rail. This dual-supply configuration is the reference design shown in the AD7607 evaluation board schematic.

Q: What is the maximum source impedance for the analog inputs?

Analog Devices specifies a maximum source impedance of 1 kΩ for full-rate 200 kSPS operation with the internal input amplifiers enabled. Above 1 kΩ, the settling time of the internal RC network exceeds the sample aperture, introducing gain error. For higher-impedance sources (e.g., 10 kΩ sensors), insert a unity-gain precision buffer op-amp with bandwidth ≥10 MHz (e.g., OPA277) before the ADC input to present a sub-1 Ω driving impedance.

Q: Does the AD7607BSTZ support FPGA direct connection without level shifting?

Yes, when DVCC is set to match the FPGA I/O voltage (2.7–5.25 V range). For a 3.3 V FPGA, tie DVCC to 3.3 V — the SCLK and CS inputs are compatible with 3.3 V LVCMOS logic at any DVCC within the allowed range. Ensure the FPGA I/O standard is configured for LVCMOS33 (not LVCMOS25 or LVTTL) to guarantee the ADC's VIH of 2.0 V is reliably exceeded.

Q: How do I daisy-chain two AD7607BSTZ devices for 16 channels?

Connect the first device's DOUT to the second device's DOUT (open-drain bus), share the same SCLK and CS lines, and use separate CONVST signals if simultaneous conversion of all 16 channels is required. After CONVST↑, both devices convert simultaneously; after BUSY↓ of the last converter, clock out 8 × 14 bits = 112 bits from the first device, then 112 bits from the second in a single SPI frame. Verify SCLK does not exceed 23 MHz and that the SPI frame length register on your MCU supports at least 224-bit transfers (or break into two 112-bit transactions with CS held low).

Q: Where can I source the AD7607BSTZ with short lead time?

Lead time and stock vary significantly across distributors. Use FindMyChip's search to query live inventory across 200+ verified distributors simultaneously. For volume orders >500 units, submit a quote request — FindMyChip's sourcing team contacts authorized distributors and provides competitive pricing within 24 hours.

Conclusion

The AD7607BSTZ delivers 8-channel simultaneous sampling with 14-bit resolution in a compact 48-LQFP package, making it one of the most capable single-chip ADC solutions for industrial motor control, power monitoring, and multi-axis sensor fusion. Key design success factors are clean AVCC regulation, careful star-ground topology, and matched RC anti-aliasing per channel. The hardware OSR feature uniquely allows firmware-selectable trade-offs between speed and resolution without changing hardware. For pin-compatible upgrades to 16-bit accuracy with 4 channels, the AD7606BSTZ-4 shares the same footprint.

Browse current stock for the AD7607BSTZ and related parts, or search across all 200+ verified distributors on FindMyChip. For project volumes or time-sensitive procurement, request a quote and receive competitive pricing within 24 hours.